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| W83977TF WINBOND I/O W83977TF Data Sheet Revision History Pages 1 2 n.a. Dates 05/20/97 Versi on 0.50 0.51 Version on Web First published. Typo correction and data calibrated Main Contents 3 4 5 IV,V,6,7,14,49,5 07/01/97 5,69-80,87-96, 103,113, 117, 118,122, 128, 149 III,3,68,134, 07/20/97 146,148; 64-67 P101,101.1,102 11/18/97 P1,3,49,62,64, 67,71,73,74, 100,117,119, 120,129 03/19/98 0.60 0.61 0.62 Explanation of OnNow/ functions; Repagenating Register correction security wake-up Typo correction and data calibrated 6 7 8 9 10 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83977TF TABLE OF CONTENTS GENERAL DESCRIPTION ....................................................................................................... 1 FEATURES.................................................................................................................................... 2 PIN CONFIGURATION ............................................................................................................. 4 1. PIN DESCRIPTION................................................................................................................ 5 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 HOST INTERFACE .....................................................................................................................................5 GENERAL PURPOSE I/O PORT...............................................................................................................7 SERIAL PORT INTERFACE......................................................................................................................8 INFRARED INTERFACE ...........................................................................................................................9 MULTI-MODE PARALLEL PORT ...........................................................................................................9 FDC INTERFACE ......................................................................................................................................14 KBC INTERFACE......................................................................................................................................15 POWER PINS .............................................................................................................................................16 ACPI INTERFACE.....................................................................................................................................16 2. FDC FUNCTIONAL DESCRIPTION ................................................................................ 17 2.1 W83977TF FDC .........................................................................................................................................17 2.1.1 AT INTERFACE.............................................................................................................................17 2.1.2 FIFO (DATA) ..................................................................................................................................17 2.1.3 DATA SEPARATOR .....................................................................................................................18 2.1.4 WRITE PRECOMPENSATION ...................................................................................................18 2.1.5 PERPENDICULAR RECORDING MODE .................................................................................18 2.1.6 FDC CORE ......................................................................................................................................19 2.1.7 FDC COMMANDS ........................................................................................................................19 2.2 REGISTER DESCRIPTIONS ...................................................................................................................29 2.2.1 STATUS REGISTER A (SA REGISTER) (READ BASE ADDRESS + 0).............................29 2.2.2 STATUS REGISTER B (SB REGISTER) (READ BASE ADDRESS + 1) .............................31 2.2.3 DIGITAL OUTPUT REGISTER (DO REGISTER) (WRITE BASE ADDRESS + 2)............33 2.2.4 TAPE DRIVE REGISTER (TD REGISTER) (READ BASE ADDRESS + 3) ........................33 2.2.5 MAIN STATUS REGISTER (MS REGISTER) (READ BASE ADDRESS + 4) ....................34 Publication Release Date: March 1998 Revision 0.62 -I- W83977TF 2.2.6 DATA RATE REGISTER (DR REGISTER) (WRITE BASE ADDRESS + 4) .......................34 2.2.7 FIFO REGISTER (R/W BASE ADDRESS + 5) ..........................................................................36 2.2.8 DIGITAL INPUT REGISTER (DI REGISTER) (READ BASE ADDRESS + 7)....................38 2.2.9 CONFIGURATION CONTROL REGISTER (CC REGISTER) (WRITE BASE ADDRESS + 7)...................................................................................................39 3. UART PORT............................................................................................................................ 40 3.1 3.2 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)..................40 REGISTER ADDRESS..............................................................................................................................40 3.2.1 UART CONTROL REGISTER (UCR) (READ/WRITE)...........................................................40 3.2.2 UART STATUS REGISTER (USR) (READ/WRITE) ...............................................................42 3.2.3 HANDSHAKE CONTROL REGISTER (HCR) (READ/WRITE) ............................................43 3.2.4 HANDSHAKE STATUS REGISTER (HSR) (READ/WRITE).................................................44 3.2.5 UART FIFO CONTROL REGISTER (UFR) (WRITE ONLY) .................................................45 3.2.6 INTERRUPT STATUS REGISTER (ISR) (READ ONLY).......................................................46 3.2.7 INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE).................................................47 3.2.8 PROGRAMMABLE BAUD GENERATOR (BLL/BHL) (READ/WRITE) .............................47 3.2.9 USER-DEFINED REGISTER (UDR) (READ/WRITE).............................................................48 4. INFRARED (IR) PORT ......................................................................................................... 49 5. PARALLEL PORT ............................................................................................................... 49 5.1 5.2 PRINTER INTERFACE LOGIC ...............................................................................................................49 ENHANCED PARALLEL PORT (EPP)..................................................................................................50 5.2.1 DATA SWAPPER ..........................................................................................................................51 5.2.2 PRINTER STATUS BUFFER.......................................................................................................51 5.2.3 PRINTER CONTROL LATCH AND PRINTER CONTROL SWAPPER...............................52 5.2.4 EPP ADDRESS PORT...................................................................................................................52 5.2.5 EPP DATA PORT 0-3....................................................................................................................53 5.2.6 BIT MAP OF PARALLEL PORT AND EPP REGISTERS .......................................................53 5.2.7 EPP PIN DESCRIPTIONS ............................................................................................................54 5.2.8 EPP OPERATION ..........................................................................................................................54 5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .....................................................................55 5.3.1 ECP REGISTER AND MODE DEFINITIONS...........................................................................55 5.3.2 DATA AND ECPAFIFO PORT....................................................................................................56 5.3.3 DEVICE STATUS REGISTER (DSR).........................................................................................56 5.3.4 DEVICE CONTROL REGISTER (DCR) ....................................................................................57 - II - Publication Release Date: March 1998 Revision 0.62 W83977TF 5.3.5 CFIFO (PARALLEL PORT DATA FIFO) MODE = 010...........................................................58 5.3.6 ECPDFIFO (ECP DATA FIFO) MODE = 011............................................................................58 5.3.7 TFIFO (TEST FIFO MODE) MODE = 110 .................................................................................58 5.3.8 CNFGA (CONFIGURATION REGISTER A) MODE = 111 ....................................................58 5.3.9 CNFGB (CONFIGURATION REGISTER B) MODE = 111.....................................................58 5.3.10 ECR (EXTENDED CONTROL REGISTER) MODE = ALL....................................................59 5.3.11 BIT MAP OF ECP PORT REGISTERS .......................................................................................60 5.3.12 ECP PIN DESCRIPTIONS ............................................................................................................61 5.3.13 ECP OPERATION..........................................................................................................................62 5.3.14 FIFO OPERATION ........................................................................................................................62 5.3.15 DMA TRANSFERS........................................................................................................................63 5.3.16 PROGRAMMED I/O (NON-DMA) MODE................................................................................63 5.4 5.5 EXTENSION FDD MODE (EXTFDD)...................................................................................................63 EXTENSION 2FDD MODE (EXT2FDD) ..............................................................................................63 6. KEYBOARD CONTROLLER .............................................................................................64 6.1 6.2 6.3 6.4 6.5 OUTPUT BUFFER ....................................................................................................................................64 INPUT BUFFER .........................................................................................................................................64 STATUS REGISTER .................................................................................................................................65 COMMANDS .............................................................................................................................................65 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC .................................................67 6.5.1 KB CONTROL REGISTER (LOGIC DEVICE 5, CR-F0) .........................................................67 6.5.2 PORT 92 CONTROL REGISTER (DEFAULT VALUE = 0X24) ............................................67 6.4 ONNOW / SECURITY KEYBOARD AND MOUSE WAKE-UP ......................................................68 7. GENERAL PURPOSE I/O....................................................................................................69 7.1 7.2 BASIC I/O FUNCTIONS...........................................................................................................................71 ALTERNATE I/O FUNCTIONS ..............................................................................................................73 7.2.1 INTERRUPT STEERING..............................................................................................................73 7.2.2 WATCH DOG TIMER OUTPUT .................................................................................................74 7.2.3 POWER LED...................................................................................................................................74 7.2.4 GENERAL PURPOSE ADDRESS DECODER..........................................................................74 7.2.5 GENERAL PURPOSE WRITE STROBE....................................................................................74 8. PLUG AND PLAY CONFIGURATION ............................................................................ 75 8.1 COMPATIBLE PNP...................................................................................................................................75 8.1.1 EXTENDED FUNCTION REGISTERS......................................................................................75 - III - Publication Release Date: March 1998 Revision 0.62 W83977TF 8.1.2 EXTENDED FUNCTIONS ENABLE REGISTERS (EFERS) .................................................76 8.1.3 EXTENDED FUNCTION INDEX REGISTERS (EFIRS), EXTENDED FUNCTION DATA REGISTERS(EFDRS) .......................................................................................................76 9. ACPI REGISTERS FEATURES ......................................................................................... 77 9.1 9.2 9.3 SMI TO SCI/SCI TO SMI AND BUS MASTER ....................................................................................78 POWER MANAGEMENT TIMER ..........................................................................................................79 ACPI REGISTERS (ACPIRS)...................................................................................................................80 9.3.1 POWER MANAGEMENT 1 STATUS REGISTER 1 (PM1STS1) ..........................................80 9.3.2 POWER MANAGEMENT 1 STATUS REGISTER 2 (PM1STS2) ..........................................81 9.3.3 POWER MANAGEMENT 1 ENABLE REGISTER 1(PM1EN1) ............................................82 9.3.4 POWER MANAGEMENT 1 ENABLE REGISTER 2 (PM1EN2) ...........................................82 9.3.5 POWER MANAGEMENT 1 CONTROL REGISTER 1 (PM1CTL1)......................................83 9.3.6 POWER MANAGEMENT 1 CONTROL REGISTER 2 (PM1CTL2)......................................83 9.3.7 POWER MANAGEMENT 1 CONTROL REGISTER 3 (PM1CTL3)......................................84 9.3.8 POWER MANAGEMENT 1 CONTROL REGISTER 4 (PM1CTL4)......................................84 9.3.9 POWER MANAGEMENT 1 TIMER 1 (PM1TMR1) ................................................................85 9.3.10 POWER MANAGEMENT 1 TIMER 2 (PM1TMR2) ................................................................85 9.3.11 POWER MANAGEMENT 1 TIMER 3 (PM1TMR3) ................................................................86 9.3.12 POWER MANAGEMENT 1 TIMER 4 (PM1TMR4) ................................................................87 9.3.13 GENERAL PURPOSE EVENT 0 STATUS REGISTER 1 (GP0STS1)...................................87 9.3.14 GENERAL PURPOSE EVENT 0 STATUS REGISTER 2 (GP0STS2)...................................88 9.3.15 GENERAL PURPOSE EVENT 0 ENABLE REGISTER 1 (GP0EN1)....................................89 9.3.16 GENERAL PURPOSE EVENT 0 ENABLE REGISTER 2 (GP0EN2)....................................89 9.3.17 GENERAL PURPOSE EVENT 1 STATUS REGISTER 1 (GP1STS1)...................................90 9.3.18 GENERAL PURPOSE EVENT 1 STATUS REGISTER 2 (GP1STS2)...................................90 9.3.19 GENERAL PURPOSE EVENT 1 ENABLE REGISTER 1 (GP1EN1)....................................91 9.3.20 GENERAL PURPOSE EVENT 1 ENABLE REGISTER 2 (GP1EN2)....................................91 9.3.21 BIT MAP CONFIGURATION REGISTERS...............................................................................92 10. SERIAL IRQ ......................................................................................................................... 93 10.1 START FRAME .........................................................................................................................................94 10.2 IRQ/DATA FRAME...................................................................................................................................94 10.3 STOP FRAME ............................................................................................................................................94 10.4 RESET AND INITIALIZATION ..............................................................................................................95 11. CONFIGURATION REGISTER.......................................................................................96 - IV - Publication Release Date: March 1998 Revision 0.62 W83977TF 11.1 CHIP (GLOBAL) CONTROL REGISTER ..............................................................................................96 11.2 LOGICAL DEVICE 0 (FDC)...................................................................................................................100 11.3 LOGICAL DEVICE 1 (PARALLEL PORT)..........................................................................................103 11.4 LOGICAL DEVICE 2 (UART A)) ........................................................................................................104 11.5 LOGICAL DEVICE 3 (UART B) ...........................................................................................................104 11.6 LOGICAL DEVICE 5 (KBC) ..................................................................................................................106 11.7 LOGICAL DEVICE 7 (GP I/O PORT I).................................................................................................107 11.8 LOGICAL DEVICE 8 (GP I/O PORT II) ...............................................................................................110 11.9 LOGICAL DEVICE 9 (GP I/O PORT III) ..............................................................................................114 11.10 LOGICAL DEVICE A (ACPI) ................................................................................................................117 12. SPECIFICATIONS ............................................................................................................123 12.1 ABSOLUTE MAXIMUM RATINGS ....................................................................................................123 12.2 DC CHARACTERISTICS .......................................................................................................................123 12.3 AC CHARACTERISTICS .......................................................................................................................127 12.3.1 FDC: DATA RATE = 1 MB, 500 KB, 300 KB, 250 KB/SEC...............................................127 12.3.2 UART/PARALLEL PORT........................................................................................................129 12.3.3 PARALLEL PORT MODE PARAMETERS ..........................................................................129 12.3.4 EPP DATA OR ADDRESS READ CYCLE TIMING PARAMETERS..............................130 12.3.5 EPP DATA OR ADDRESS WRITE CYCLE TIMING PARAMETERS ............................131 12.3.6 PARALLEL PORT FIFO TIMING PARAMETERS..............................................................132 12.3.7 ECP PARALLEL PORT FORWARD TIMING PARAMETERS.........................................132 12.3.8 ECP PARALLEL PORT REVERSE TIMING PARAMETERS ...........................................132 12.3.9 KBC TIMING PARAMETERS ................................................................................................133 12.3.10 GPIO TIMING PARAMETERS................................................................................................134 13. TIMING WAVEFORMS ..................................................................................................135 13.1 FDC ............................................................................................................................................................135 13.2 UART/PARALLEL...................................................................................................................................136 13.2.1 MODEM CONTROL TIMING ................................................................................................137 13.3 PARALLEL PORT ...................................................................................................................................138 13.3.1 PARALLEL PORT TIMING.....................................................................................................138 13.3.2 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.9)......................................139 13.3.3 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.9) ....................................140 13.3.4 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.7)......................................141 13.3.5 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.7) ....................................142 13.3.6 PARALLEL PORT FIFO TIMING...........................................................................................142 -V- Publication Release Date: March 1998 Revision 0.62 W83977TF 13.3.7 ECP PARALLEL PORT FORWARD TIMING......................................................................143 13.3.8 ECP PARALLEL PORT REVERSE TIMING........................................................................143 13.4 KBC............................................................................................................................................................144 13.4.1 WRITE CYCLE TIMING..........................................................................................................144 13.4.2 READ CYCLE TIMING ...........................................................................................................144 13.4.3 SEND DATA TO K/B...............................................................................................................144 13.4.4 RECEIVE DATA FROM K/B ..................................................................................................145 13.4.5 INPUT CLOCK..........................................................................................................................145 13.4.6 SEND DATA TO MOUSE.......................................................................................................145 13.4.7 RECEIVE DATA FROM MOUSE ..........................................................................................145 13.5 GPIO WRITE TIMING DIAGRAM .......................................................................................................146 13.6 MASTER RESET (MR) TIMING...........................................................................................................146 14. APPLICATION CIRCUITS .............................................................................................147 14.1 PARALLEL PORT EXTENSION FDD.................................................................................................147 14.2 PARALLEL PORT EXTENSION 2FDD...............................................................................................147 14.3 FOUR FDD MODE ..................................................................................................................................148 15. ORDERING INFORMATION.........................................................................................148 16. HOW TO READ THE TOP MARKING .......................................................................148 17. PACKAGE DIMENSIONS...............................................................................................149 - VI - Publication Release Date: March 1998 Revision 0.62 W83977TF WINBOND I/O GENERAL DESCRIPTION The W83977TF is an evolving product from Winbond's most popular I/O chip W83877F --- which integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plug-andplay registers for the whole chip --- plus additional powerful features: ACPI, 8042 keyboard controller with PS/2 mouse support, 23 general purpose I/O ports, full 16-bit address decoding, OnNow keyboard wake-up, OnNow mouse wake-up. The disk drive adapter functions of W83977TF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated into the W83977TF greatly reduces the number of components required for interfacing with floppy disk drives. The W83977TF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83977TF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. The W83977TF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature TM demand of Windows 95 , which makes system resource allocation more efficient than ever. W83977TF provides functions that comply with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through SMI or SCI function pins. W83977TF also has auto power management to reduce power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM TM and a 256-Byte RAM bank. Keyboard BIOS firmware is available with optional AMIKEY -2, Phoenix TM MultiKey/42 , or customer code. The W83977TF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. W83977TF is made to fully comply with Microsoft PC97 Hardware Design Guide. IRQs, DMAs, and I/O space resource are flexible to adjust to meet ISA PnP requirement. Moreover W83977TF is made to meet the specification of PC97's requirement in the power management: ACPI and DPM (Device Power Management). Another benifit is that W83977TF has the same pin assignment as W83977AF, W83977F, W83977ATF. This makes the design very flexible. -1- Publication Release Date: April 1998 Preliminary Revision 0.62 W83977TF PRELIMINARY FEATURES General * Plug & Play 1.0A compatible * Support 13 IRQs, 4 DMA channels, full 16-bit address decoding * Capable of ISA Bus IRQ Sharing * Compliant with Microsoft PC97 Hardware Design Guide * Support DPM (Device Power Management), ACPI * Report ACPI status interrupt by SCI signal issued from any of the 13 IQRs pins or GPIO xx * Programmable configuration settings * Single 24/48 Mhz clock input FDC * Compatible with IBM PC AT disk drive systems * Variable write pre-compensation with track selectable capability * Support vertical recording format * DMA enable logic * 16-byte data FIFOs * Support floppy disk drives and tape drives * Detects all overrun and underrun conditions * Built-in address mark detection circuit to simplify the read electronics * FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) * Support up to four 3.5-inch or 5.25-inch floppy disk drives * Completely compatible with industry standard 82077 * 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate * Support 3-mode FDD, and its Win95 driver UART * Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs * MIDI compatible * Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation * Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation * Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz Publication Release Date: April 1998 Revision 0.62 -2- W83977TF PRELIMINARY Infrared * Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps * Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps * Support S/W driver for Windows95TM and Windows98TM (MemphisTM) Parallel Port * Compatible with IBM parallel port * Support PS/2 compatible bi-directional parallel port * Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification * Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification * Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port * Enhanced printer port back-drive current protection Keyboard Controller * 8042 based with optional F/W from AMIKKEY -2, Phoenix MultiKey/42 with 2K bytes of programmable ROM, and 256 bytes of RAM * Asynchronous Access to Two Data Registers and One status Register * Software compatibility with the 8042 and PC87911 microcontrollers * Support PS/2 mouse * Support port 92 * Support both interrupt and polling modes * Fast Gate A20 and Hardware Keyboard Reset * 8 Bit Timer/ Counter * Support binary and BCD arithmetic * 6MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency TM TM or customer code General Purpose I/O Ports * 23 programmable general purpose I/O ports; 3 dedicate, 20 optional * General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins OnNow Funtions * Keyboard wake-up by programmable keys * Mouse wake-up by programmable buttons Package * 128-pin PQFP -3 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY PIN CONFIGURATION / /P PA AN NS SW WO IU NT ,, IIII GG R R R RA V A A A A V A P PV Q Q Q Q1 S 1 1 1 1 C 1 A A A A A A A A A A 2 2 S 6 7 8 95 S 4 3 2 1 C0 9 8 7 6 5 4 3 2 1 0 3 2 B II RR QQ 11 21 I RI I I I QR R R R 1 QQQ Q 0134 5 / S M I, G GMK P PCC 22LL 1 0KK / R I B / R I A 11 199 9 9 999999 88 8888888877 7777777 766666 00 098 7 6 543210 98 7654321098 7654321 098765 210 IRQ14/GP14 IRQ15/GP15 IOR IOW AEN IOCHRDY D0 D1 D2 D3 D4 D5 VCC D6 D7 MR DACK0/GP16 VSS SCI/DRQ0/GP17 DACK1 DRQ1 DACK2 DRQ2 DACK3 DRQ3 TC 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 11 11 1 1 1 1 1 22 22 2 222 2 2 3 33 3 3 33 33 1 2 34 5 67 8 90 12 34 5 6 7 8 9 01 23 4 567 8 9 0 12 3 4 56 78 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VBAT XTAL1 VSS XTAL2 MDATA KDATA KBLOCK/GP13 KBRST/GP12 GA20/GP11 VCC DCDB SOUTB/PEN48 SINB DTRB RTSB DSRB CTSB DCDA SOUTA/PENKBC SINA DTRA/PNPCSV RTSA/HEFRAS DSRA CTSA GP24 GP25 C L K I N D R V D E N 0 D/ / / / / / / / R D H R W T WW S VS E DP R E D T DK A A A E ECDT K P NH A 0 1G , G P 1 0 , / S C I / D I R /// MDD OSS BAB / / S P V B / PP V P P P PP P / / / / M I L E C U A DD S D D D DD DS I E A O NC C S C 7 6 S 5 4 3 2 1 0 L N RF I I RD A DT YK E NT X / S T B I R R X I R T X -4- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1. PIN DESCRIPTION Note: Please refer to Section 11.2 DC CHARACTERISTICS for details. I/O6t - TTL level bi-directional pin with 6 mA source-sink capability I/O8t - TTL level bi-directional pin with 8 mA source-sink capability I/O8 - CMOS level bi-directional pin with 8 mA source-sink capability I/O12t - TTL level bi-directional pin with 12 mA source-sink capability I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability I/O16u - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor I/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor I/O24t - TTL level bi-directional pin with 24 mA source-sink capability OUT8t - TTL level output pin with 8 mA source-sink capability OUT12t - TTL level output pin with 12 mA source-sink capability OD12 - Open-drain output pin with 12 mA sink capability OD24 - Open-drain output pin with 24 mA sink capability INt - TTL level input pin INc - CMOS level input pin INcu - CMOS level input pin with internal pull-up resitor INcs - CMOS level Schmitt-triggered input pin INts - TTL level Schmitt-triggered input pin INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor 1.1 Host Interface SYMBOL A0-A10 A11-A14 A15 D0-D5 D6-D7 IOR IOW PIN 74-84 86-89 91 109114 116117 105 106 107 108 118 I/O INt INt INt I/O12t I/O12t INts INts INts OD24 INts FUNCTION System address bus bits 0-10 System address bus bits 11-14 System address bus bit 15 System data bus bits 0-5 System data bus bits 6-7 CPU I/O read signal CPU I/O write signal System address bus enable In EPP Mode, this pin is the IO Channel Ready output to extend the host read/write cycle. Master Reset; Active high; MR is low during normal operations. AEN IOCHRDY MR -5 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.1 Host Interface, continued SYMBOL DACK0 GP16 (WDTO) P15 DRQ0 GP17 (PLEDO) P14 SCI DACK1 DRQ1 DACK2 DRQ2 DACK3 DRQ3 TC IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 PIN 119 I/O INtsu I/O12t I/O12t FUNCTION DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00, default) General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01) Alternate function from GP16: Watch dog timer output KBC P15 I/O port. (CR2C bit 5_4 = 10) DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default) General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01) Alternate Function from GP17: Power LED output. KBC P14 I/O port (CR2C bit 7_6 = 10) System Control Interrupt (CR2C bit 7_6 = 11) DMA Channel 1 Acknowledge signal DMA Channel 1 request signal DMA Channel 2 Acknowledge signal DMA Channel 2 request signal DMA Channel 3 Acknowledge signal DMA Channel 3 request signal Terminal Count. When active, this pin indicates termination of a DMA transfer. Interrupt request 1 Interrupt request 3 Interrupt request 4 Interrupt request 5 Interrupt request 6 Interrupt request 7 Interrupt request 8 Interrupt request 9 Interrupt request 10 Interrupt request 11 Interrupt request 12 121 OUT12t I/O12t I/O12t OUT12t 122 123 124 125 126 127 128 99 98 97 96 95 94 93 92 100 101 102 INts OUT12t INts OUT12t INts OUT12t INts OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t -6- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.1 Host Interface, continued SYMBOL IRQ14 GP14 ( GPACS ) (P17) PLEDO IRQ15 GP15 ( GPAWE ) (P12) WDT CLKIN PIN 103 I/O OUT12t I/O12t FUNCTION Interrupt request 14. (CR2C bit 1_0 = 00, default) General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01) Alternate Function 1 from GP14: General purpose address decode output. Alternate Function 2 from GP14: KBC P17 I/O port. OUT12t 104 OUT12t I/O12t Power LED output. (CR2C bit 1_0 = 10) Interrupt request 15.(CR2C bit 3_2 = 00, default) General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01) Alternate Function 1 from GP15: General purpose address write enable output. Alternate Function 2 from GP15: KBC P12 I/O port. OUT12t 1 INt Watch-Dog timer output. (CR2C bit 3_2 = 10) 24 or 48 MHz clock input, selectable through bit 5 of CR24. 1.2 General Purpose I/O Port SYMBOL GP20 (KBRST) SMI PIN 69 70 I/O I/O12t OUT12t FUNCTION General purpose I/O port 2 bit 0. Alternate Function from GP20: Keyboard reset (KBC P20) For the power management, the SMI is active low by the power management events, that generate and SCI in ACPI mode. (CR2B bit 4_3 = 00, default) General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01) Alternate Function from GP21: KBC P13 I/O port. I/O12t 72 OUT12t I/O12t IN12t I/O12t I/O12t I/O12t 39 I/O12 KBC P16 I/O port. (CR2B bit 4_3 = 10) Panel Switch output. (CR2B bit 5 = 0, default) General purpose I/O port 2 bit 2. (CR2B bit 5 = 1) Alternate Function from GP22: KBC P14 I/O port. Panel Switch input. (CR2B bit 7_6 = 00, default) General purpose I/O port 2 bit 3. (CR2B bit 7_6 = 01) Alternate Function from GP23: KBC P15 I/O port 40 General purpose I/O port 2 bit 4 (CR2A bit 5_4 = 01) Alternate Function from GP24: KBC P16 I/O port KBC P13 I/O port. (CR2A bit 5_4 = 10) General purpose I/O port 2 bit 5. Alternate Function from GP25: GATE A20 (KBC P21) GP21 (P13) P16 PANSWOUT GP22 (P14) PANSWIN GP23 (P15) GP24 (P16) P13 GP25 (GA20) I/O12t 73 -7 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.3 Serial Port Interface SYMBOL CTSA CTSB DSRA DSRB RTSA PIN 41 48 42 49 43 I/O8t INt I/O INt FUNCTION Clear To Send is the modem control input. The function of these pins can be tested by reading Bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k is recommended if intends to pull up. (select 370H as configuration I/O ports address) 50 44 I/O8t I/O8t UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV , which provides the power-on value for CR24 bit 0 (PNPCSV ). A 4.7 k is recommended if intends to pull up. (clear the default value of FDC, UARTs, and PRT) DTRB SINA SINB SOUTA PENKBC 51 I/O8t UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. Used to receive serial data through the communication link. UART A Serial Output. Used to transmit serial data out to the communication link. During power-on reset, this pin is pulled down internally and is defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 k resistor is recommended if intends to pull up. (enable KBC) 53 I/O8t UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 k resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. HEFRAS RTSB DTRA PNPCSV 45, 52 46 INt I/O8t SOUTB PEN48 DCDA DCDB 47 54 INt -8- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.3 Serial Port Interface, continued SYMBOL RIA RIB PIN 65 66 I/O INt FUNCTION Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. 1.4 Infrared Interface SYMBOL IRRX IRTX PIN 37 38 I/O INcs OUT12t FUNCTION Infrared Receiver input. Infrared Transmitter Output. 1.5 Multi-Mode Parallel Port The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL SLCT PIN 18 I/O INt PRINTER MODE: SLCT An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: WE2 This pin is for Extension FDD B; its function is the same as the WE pin of FDC. OD12 EXTENSION 2FDD MODE: WE2 This pin is for Extension FDD A and B; it function is the same as the WE pin of FDC. PE 19 INt PRINTER MODE: PE An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: WD2 This pin is for Extension FDD B; its function is the same as the WD pin of FDC. OD12 EXTENSION 2FDD MODE: WD2 This pin is for Extension FDD A and B; its function is the same as the WD pin of FDC. FUNCTION -9 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.5 Multi-Mode Parallel Port, continued SYMBOL BUSY PIN 21 I/O INt PRINTER MODE: BUSY FUNCTION An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: MOB2 This pin is for Extension FDD B; the function of this pin is the same as the MOB pin of FDC. OD12 EXTENSION 2FDD MODE: MOB2 This pin is for Extension FDD A and B; the function of this pin is the same as the MOB pin of FDC. ACK 22 INt PRINTER MODE: ACK An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DSB2 This pin is for the Extension FDD B; its functions is the same as the DSB pin of FDC. OD12 EXTENSION 2FDD MODE: DSB2 This pin is for Extension FDD A and B; it functions is the same as the DSB pin of FDC. ERR 34 INt PRINTER MODE: ERR An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 OD12 EXTENSION FDD MODE: HEAD2 This pin is for Extension FDD B; its function is the same as the HEADpin of FDC. EXTENSION 2FDD MODE: HEAD2 This pin is for Extension FDD A and B; its function is the same as the HEAD pin of FDC. -10- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.5 Multi-Mode Parallel Port, continued SYMBOL SLIN PIN 32 I/O OD12 PRINTER MODE: SLIN FUNCTION Output line for detection of printer selection. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: STEP2 This pin is for Extension FDD B; its function is the same as the STEP pin of FDC. OD12 EXTENSION 2FDD MODE: STEP2 This pin is for Extension FDD A and B; its function is the same as the STEP pin of FDC. INIT 33 OD12 PRINTER MODE: INIT Output line for the printer initialization. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DIR2 This pin is for Extension FDD B; its function is the same as the DIR pin of FDC. OD12 EXTENSION 2FDD MODE: DIR2 This pin is for Extension FDD A and B; its function is the same as the DIR pin of FDC. PRINTER MODE: AFD An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. OD12 EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. AFD 35 OD12 -11 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.5 Multi-Mode Parallel Port, continued SYMBOL STB PIN 36 I/O OD12 PRINTER MODE: STB FUNCTION An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. PD0 31 I/O24t EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: INDEX2 This pin is for Extension FDD B; the function of this pin is the same as the INDEX pin of FDC. It is pulled high internally. INt EXTENSION 2FDD MODE: INDEX2 This pin is for Extension FDD A and B; the function of this pin is the same as the INDEX pin of FDC. It is pulled high internally. PD1 30 I/O24t PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: TRAK02 This pin is for Extension FDD B; the function of this pin is the same as the TRAK 0 pin of FDC. It is pulled high internally. INt EXTENSION. 2FDD MODE: TRAK02 This pin is for Extension FDD A and B; the function of this pin is the same as the TRAK 0 pin of FDC. It is pulled high internally. PD2 29 I/O24t PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: WP2 This pin is for Extension FDD B; the function of this pin is the same as the WP pin of FDC. It is pulled high internally. INt EXTENSION. 2FDD MODE: WP2 This pin is for Extension FDD A and B; the function of this pin is the same as the WP pin of FDC. It is pulled high internally. -12- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.5 Multi-Mode Parallel Port, continued SYMBOL PD3 PIN 28 I/O I/O24t FUNCTION PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2 This pin is for Extension FDD B; the function of this pin is the same as the RDATA pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: RDATA2 This pin is for Extension FDD A and B; this function of this pin is the same as the RDATA pin of FDC. It is pulled high internally. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSKCHG2 This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2 This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG pin of FDC. It is pulled high internally. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. INt INt PD4 27 I/O24t INt INt PD5 26 I/O24t PD6 24 I/O24t - OD24 EXTENSION. 2FDD MODE: MOA2 This pin is for Extension FDD A; its function is the same as the MOA pin of FDC. -13 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.5 Multi-Mode Parallel Port, continued SYMBOL PD7 PIN 23 I/O I/O24t PRINTER MODE: PD7 FUNCTION Parallel port data bus bit 7. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD24 EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2 This pin is for Extension FDD A; its function is the same as the DSA pin of FDC. 1.6 FDC Interface SYMBOL DRVDEN0 DRVDEN1 GP10 (IRQIN1) P12 SCI HEAD 5 IO24t OUT12t OD24 PIN 2 3 I/O OD24 OD24 IO24t Drive Density Select bit 0. Drive Density Select bit 1. (CR2A bit 1_0 = 00, default) General purpose I/O port 1 bit 0. (CR2A bit 1_0 = 01) Alternate Function from GP10: Interrupt channel input. KBC P12 I/O port. (CR2A bit 1_0 = 10) System Control Interrupt (CR2A bit 1_0 = 11) Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Write enable. An open drain output. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Step output pulses. This active low open drain output produces a pulse to move the head to another track. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion MOB DSA DSB 13 14 15 OD24 OD24 OD24 Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. FUNCTION WE WD STEP DIR 9 10 11 12 OD24 OD24 OD24 OD24 -14- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.6 FDC Interface, continued SYMBOL MOA DSKCHG PIN 16 4 I/O OD24 INcs FUNCTION Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). RDATA 6 INcs WP 7 INcs TRAK0 8 INcs INDEX 17 INcs 1.7 KBC Interface SYMBOL KDATA MDATA KCLK MCLK GA20 GP11 (IRQIN2) KBRST GP12 (WDTO) 57 I/O12t I/O12t PIN 59 60 67 68 56 I/O I/OD16u I/OD16u I/OD16u I/OD16u I/O12t I/O12t Keyboard Data PS2 Mouse Data Keyboard Clock PS2 Mouse Clock KBC GATE A20 (P21) Output. (CR2A bit 6 = 0, default) General purpose I/O port 1 bit 1. (CR2A bit 6 = 1) Alternate Function from GP11: Interrupt channel input. W83C45 Keyboard Reset (P20) Output. (CR2A bit 7 = 0, default) General purpose I/O port 1 bit 2. (CR2A bit 7 = 1) Alternate Function 1 from GP12 : Watchdog timer output. FUNCTION -15 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 1.7 KBC Interface, continued SYMBOL KBLOCK GP13 PIN 58 I/O INts I/O16t FUNCTION W83C45 KINH (P17) Input. (CR2B bit 0 = 0, default) General purpose I/O port 1 bit 3. (CR2B bit 0 = 1) 1.8 POWER PINS SYMBOL VCC VSB GND PIN 20, 55, 85, 115 71 25, 62, 90, 120 FUNCTION +5V power supply for the digital circuitry +5V stand-by power supply for the digital circuitry Ground 1.9 ACPI Interface SYMBOL VBAT XTAL1 XTAL2 PIN 64 63 61 I/O NA INC O8t battery voltage input 32.768Khz Clock Input 32.768Khz Clock Output FUNCTION -16- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 2. FDC FUNCTIONAL DESCRIPTION 2.1 W83977TF FDC The floppy disk controller of the W83977TF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 2 M bits/sec data rate. The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core. 2.1.1 AT interface The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT. 2.1.2 FIFO (Data) The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula: THRESHOLD # x (1/DATA/RATE) *8 - 1.5 S = DELAY FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 x 16 S - 1.5 S = 14.5 S 2 x 16 S - 1.5 S = 30.5 S 8 x 16 S - 1.5 S = 6.5 S 15 x 16 S - 1.5 S = 238.5 S MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 x 8 S - 1.5 S = 6.5 S 2 x 8 S - 1.5 S = 14.5 S 8 x 8 S - 1.5 S = 62.5 S 15 x 8 S - 1.5 S = 118.5 S -17 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred. An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK and addresses need not be valid. Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by the FDC based only on DACK . This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed. 2.1.3 Data Separator The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes. The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream. 2.1.4 Write Precompensation The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. 2.1.5 Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area. FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. -18- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 2.1.6 FDC Core The W83977TF FDC is capable of performing twenty commands. Each command is initiated by a multibyte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided to the microprocessor. 2.1.7 FDC Commands Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out DIR = 1, step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EOT: End of Track EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of track FIFOTHR: FIFO Threshold GAP: Gap length selection GPL: Gap Length H: Head number HDS: Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten PCN: Present Cylinder Number POLL: Polling Disable PRETRK: Precompensation Start Track Number Publication Release Date: April 1998 Revision 0.62 -19 - W83977TF PRELIMINARY R: RCN: R/W: SC: SK: SRT: ST0: ST1: ST2: ST3: WG: Record Relative Cylinder Number Read/Write Sector/per cylinder Skip deleted data address mark Step Rate Time Status Register 0 Status Register 1 Status Register 2 Status Register 3 Write gate alters timing of WE (1) Read Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 0 D6 0 D5 SK D4 0 0 D3 0 0 D2 1 D1 1 D0 0 REMARKS Command codes Sector ID information prior to command execution MT MFM HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system Status information after command execution -20- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY (2) Read Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 D6 D5 SK 0 D4 0 0 D3 1 0 D2 1 0 D1 0 D0 REMARKS Command codes MT MFM 0 0 HDS DS1 DS0 Sector ID information prior to command execution ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system Status information after command execution -21 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY (3) Read A Track PHASE Command R/W W W W W W W W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 0 0 D3 0 D2 1 D1 0 D0 REMARKS Command codes HDS DS1 DS0 Sector ID information prior to command execution ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution Status information after command execution Result -22- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY (4) Read ID PHASE Command R/W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 0 D3 1 0 D2 1 D1 0 D0 REMARKS Command codes HDS DS1 DS0 The first correct ID information on the cylinder is stored in Data Register Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------ Status information after command execution Disk status after the command has been completed (5) Verify PHASE Command R/W W W W W W W W W D7 EC D6 0 D5 0 D4 1 0 D3 0 0 D2 1 1 D1 0 D0 REMARKS Command codes Sector ID information prior to command execution MT MFM SK HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL/SC ------------------- Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------ No data transfer takes place Status information after command execution Sector ID information after command execution -23 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY (6) Version PHASE Command Result (7) Write Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after Command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 0 0 D2 1 D1 0 1 D0 REMARKS Command codes Sector ID information prior to Command execution R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 0 0 D1 0 0 D0 REMARKS Command code Enhanced controller MT MFM HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system Status information after Command execution -24- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY (8) Write Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 1 0 0 D2 0 D1 1 D0 REMARKS Command codes Sector ID information prior to command execution MT MFM HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system Status information after command execution -25 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY (9) Format A Track PHASE Command R/W W W W W W W Execution for Each Sector Repeat: Result W W W W R R R R R R R D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 1 D2 0 D1 1 D0 REMARKS Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters HDS DS1 DS0 ---------------------- N -------------------------------------------- SC ------------------------------------------- GPL ------------------------------------------ D --------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ------------------- Status information after command execution (10) Recalibrate PHASE Command R/W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 0 D3 0 0 D2 1 1 D1 1 D0 REMARKS Command codes DS1 DS0 Head retracted to Track 0 Interrupt (11) Sense Interrupt Status PHASE Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 0 D2 0 D1 0 D0 REMARKS Command code Status information at the end of each seek operation ---------------- ST0 ---------------------------------------- PCN ------------------------- -26- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY (12) Specify PHASE Command R/W W W W D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 1 D1 1 D0 REMARKS Command codes | ---------SRT ----------- | --------- HUT ---------- | |------------ HLT ----------------------------------| ND (13) Seek PHASE Command R/W W W W Execution R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 1 D2 1 D1 1 D0 REMARKS Command codes HDS DS1 DS0 Head positioned over proper cylinder on diskette -------------------- NCN ----------------------- (14) Configure PHASE Command R/W W W W W Execution D7 0 0 0 D6 0 0 D5 0 0 D4 1 0 D3 0 0 0 0 D2 1 0 D1 1 0 D0 REMARKS Configure information EIS EFIFO POLL | ------ FIFOTHR ----| Internal registers written | --------------------PRETRK ----------------------- | (15) Relative Seek PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 1 D2 1 D1 1 D0 REMARKS Command codes HDS DS1 DS0 | -------------------- RCN ---------------------------- | -27 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY (16) Dumpreg PHASE Command Result R/W W R R R R R R R R R R D7 0 D6 0 D5 0 D4 0 1 D3 1 D2 1 D1 0 D0 REMARKS Registers placed in FIFO ----------------------- PCN-Drive 0------------------------------------------ PCN-Drive 1 ----------------------------------------- PCN-Drive 2------------------------------------------ PCN-Drive 3 --------------------------SRT ------------------ | --------- HUT ------------------ HLT -----------------------------------| ND ------------------------ SC/EOT ---------------------LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS EFIFO POLL | ------ FIFOTHR ------------------------------PRETRK ------------------------- (17) Perpendicular Mode PHASE Command R/W W W (18) Lock PHASE Command Result R/W W R D7 0 D6 0 D5 0 0 D4 1 LOCK D3 0 0 1 0 D2 0 0 D1 0 0 D0 REMARKS Command Code D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 1 D1 0 D0 REMARKS Command Code D0 GAP WG LOCK 0 (19) Sense Drive Status PHASE Command Result R/W W W R D7 0 0 D6 0 0 D5 0 0 D4 0 0 0 D3 0 D2 1 0 D1 0 D0 REMARKS Command Code Status information about disk drive HDS DS1 DS0 ---------------- ST3 ------------------------- (20) Invalid PHASE Command Result R/W W R D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Invalid codes (no operationFDC goes to standby state) ST0 = 80H ------------- Invalid Codes ------------------------------------ ST0 ---------------------- -28- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 2.2 Register Descriptions There are several status, data, and control registers in W83977TF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 READ SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER REGISTER WRITE DO REGISTER TD REGISTER DR REGISTER DT (FIFO) REGISTER CC REGISTER 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 DIR WP INDEX HEAD TRAK0 STEP DRV2 INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRV 2 (Bit 6): 0 1 A second drive has been installed A second drive has not been installed STEP (Bit 5): This bit indicates the complement of STEP output. TRAK0 (Bit 4): This bit indicates the value of TRAK0 input. HEAD (Bit 3): -29 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY This bit indicates the complement of HEAD output. 0 1 side 0 side 1 INDEX (Bit 2): This bit indicates the value of INDEX output. WP (Bit 1): 0disk is write-protected 1disk is not write-protected DIR (Bit 0) This bit indicates the direction of head movement. 0 1 outward direction inward direction In PS/2 Model 30 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0 input. HEAD (Bit 3): This bit indicates the value of HEAD output. 0 side 1 1 side 0 Publication Release Date: April 1998 Revision 0.62 -30- W83977TF PRELIMINARY INDEX (Bit 2): This bit indicates the complement of INDEX output. WP (Bit 1): 0 1 disk is not write-protected disk is write-protected DIR (Bit 0) This bit indicates the direction of head movement. 0 1 inward direction outward direction 2.2.2 Status Register B (SB Register) (Read base address + 1) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 7 1 6 1 MOT EN A MOT EN B WE RDATA Toggle WDATA Toggle Drive SEL0 5 4 3 2 1 0 Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA output pin. WE (Bit 2): This bit indicates the complement of the WE output pin. MOT EN B (Bit 1) This bit indicates the complement of the MOB output pin. MOT EN A (Bit 0) This bit indicates the complement of the MOA output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows: Publication Release Date: April 1998 Revision 0.62 -31 - W83977TF PRELIMINARY 7 6 5 4 3 2 1 0 DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 DRV2 (Bit 7): 0 1 A second drive has been installed A second drive has not been installed DSB (Bit 6): This bit indicates the status of DSB output pin. DSA (Bit 5): This bit indicates the status of DSA output pin. WD F/F(Bit 4): This bit indicates the complement of the latched WD output pin at every rising edge of the WD output pin. RDATA F/F(Bit 3): This bit indicates the complement of the latched RDATA output pin . WE F/F (Bit 2): This bit indicates the complement of latched WE output pin. DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected -32- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 2.2.3 Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows: 7 6 5 4 3 2 1-0 Drive Select: 00 select drive A 01 select drive B 10 select drive C 11 select drive D Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high 2.2.4 Tape Drive Register (TD Register) (Read base address + 3) This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows: 7 X 6 X 5 X 4 X 3 X 2 X Tape sel 0 Tape sel 1 1 0 If three mode FDD function is enabled (EN3MODE = 1 in Logical Device 0 CRF0 bit:0), the bit definitions are as follows: 7 6 5 4 3 2 1 0 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 -33 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of Logical Device 0 CRF1 bit 4,5. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of Logical Device 0 CRF2. Which two bits are reflected depends on the last drive selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of Logical Device 0 CRF1 bit 7,6. Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. TAPE SEL 1 0 0 1 1 TAPE SEL 0 0 1 0 1 DRIVE SELECTED None 1 2 3 2.2.5 Main Status Register (MS Register) (Read base address + 4) The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode. FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. 2.2.6 Data Rate Register (DR Register) (Write base address + 4) The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER. -34- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 7 6 5 0 DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET 4 3 2 1 0 S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits. PRECOMP 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 PRECOMPENSATION DELAY 250K - 1 Mbps 2 Mbps Tape drive Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled) -35 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67nS 20.8 nS DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1 01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0 10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0 11 1 MB/S (MFM), Illegal (FM), RWC = 1 The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual data rates setting. 2.2.7 FIFO Register (R/W base address + 5) The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83977TF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. Status Register 0 (ST0) 7-6 5 4 3 2 1-0 US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ready EC Equipment Check: 1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error SE Seek end: 1 seek end 0 seek error IC Interrupt Code: 00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue 11 Abnormal termination because the ready signal from FDD changed state during command execution -36- Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY Status Register 1 (ST1) 7 6 5 4 3 2 1 0 Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder. Status Register 2 (ST2) 7 6 5 4 3 2 1 0 MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field) 1 If the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0 Status Register 3 (ST3) 7 6 5 4 3 2 1 0 US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault -37 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 2.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of DSKCHG , while other bits of the data bus remain in tri-state. Bit definitions are as follows: 7 6 5 4 3 2 1 0 x x x x xxx for hard disk controller x Reservedreadthe this register, these bits are in tri-state During a of DSKCHG In the PS/2 mode, the bit definitions are as follows: 7 6 1 5 1 4 1 3 1 HIGH DENS DRATE0 DRATE1 2 1 0 DSKCHG DSKCHG (Bit 7): This bit indicates the complement of the DSKCHG input. Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates. HIGH DENS (Bit 0): 0 500 KB/S or 1 MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate In the PS/2 Model 30 mode, the bit definitions are as follows: 7 6 0 5 0 4 0 DRATE0 DRATE1 NOPREC DMAEN 3 2 1 0 DSKCHG DSKCHG (Bit 7): Publication Release Date: April 1998 Revision 0.62 -38- W83977TF PRELIMINARY This bit indicates the status of DSKCHG input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. 2.2.9 Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows: 7 6 5 4 3 2 1 0 x x x x x x DRATE0 DRATE1 X: Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows: 7 X 6 X 5 X 4 X 3 X DRATE0 DRATE1 NOPREC 2 1 0 X: Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. -39 - Publication Release Date: April 1998 Revision 0.62 W83977TF PRELIMINARY 3. UART PORT 3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode. 3.2 Register Address 3.2.1 UART Control Register (UCR) (Read/Write) The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection. 7 6 5 4 3 2 1 0 Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed. Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check. - 40 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY TABLE 3-1 UART Register Bit Map Bit Number Register Address Base +0 BDLAB = 0 Receiver Buffer Register (Read Only) RBR 0 RX Data Bit 0 1 RX Data Bit 1 2 RX Data Bit 2 3 RX Data Bit 3 4 RX Data Bit 4 5 RX Data Bit 5 6 RX Data Bit 6 7 RX Data Bit 7 +0 Transmitter BDLAB = 0 Buffer Register (Write Only) +1 BDLAB = 0 Interrupt Control Register TBR TX Data Bit 0 TX Data Bit 1 TBR Empty Interrupt Enable (ETBREI) Interrupt Status Bit (0) TX Data Bit 2 USR Interrupt Enable (EUSRI) Interrupt Status Bit (1) XMIT FIFO Reset Multiple Stop Bits Enable (MSBE) Loopback RI Input Parity Bit Error (PBER) RI Falling Edge (FERI) Bit 2 Bit 2 TX Data Bit 3 HSR Interrupt Enable (EHSRI) Interrupt Status Bit (2)** DMA Mode Select Parity Bit Enable (PBE) IRQ Enable TX Data Bit 4 0 TX Data Bit 5 0 TX Data Bit 6 0 TX Data Bit 7 0 ICR RBR Data Ready Interrupt Enable (ERDRI) "0" if Interrupt Pending +2 Interrupt Status Register (Read Only) UART FIFO Control Register (Write Only) UART Control Register ISR 0 0 FIFOs Enabled ** FIFOs Enabled ** RX Interrupt Active Level (MSB) Baudrate Divisor Latch Access Bit (BDLAB) 0 +2 UFR FIFO Enable RCVR FIFO Reset Data Length Select Bit 1 (DLS1) Request to Send (RTS) Overrun Error (OER) DSR Toggling (TDSR) Bit 1 Bit 1 Reserved Reversed RX Interrupt Active Level (LSB) Set Silence Enable (SSE) 0 +3 UCR Data Length Select Bit 0 (DLS0) Data Terminal Ready (DTR) RBR Data Ready (RDR) Even Parity Enable (EPE) Internal Loopback Enable Silent Byte Detected (SBD) Clear to Send (CTS) Bit 4 Bit 4 Parity Bit Fixed Enable PBFE) 0 +4 Handshake Control Register UART Status Register HCR +5 USR No Stop Bit Error (NSER) DCD Toggling (TDCD) Bit 3 Bit 3 TBR Empty (TBRE) Data Set Ready (DSR) Bit 5 Bit 5 TSR Empty (TSRE) Ring Indicator (RI) Bit 6 Bit 6 RX FIFO Error Indication (RFEI) ** Data Carrier Detect (DCD) Bit 7 Bit 7 +6 Handshake Status Register User Defined Register Baudrate Divisor Latch Low Baudrate Divisor Latch High HSR CTS Toggling (TCTS) Bit 0 Bit 0 +7 +0 BDLAB = 1 +1 BDLAB = 1 UDR BLL BHL Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode. - 41 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked. Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected. Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked. Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character. TABLE 3-2 WORD LENGTH DEFINITION DLS1 0 0 1 1 DLS0 0 1 0 1 DATA LENGTH 5 bits 6 bits 7 bits 8 bits 3.2.2 UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of the data transfer during communication. 7 6 5 4 3 2 1 0 RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO. Publication Release Date: March 1998 Revision 0.62 - 42 - W83977TF PRELIMINARY Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese two cases, this bit will be reset to a logical 0. Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO. Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. 3.2.3 Handshake Control Register (HCR) (Read/Write) This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART. 7 0 6 0 5 0 Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable 4 3 2 1 0 - 43 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as follows: (1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the TSR. (2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR (bit 0 of HCR) DSR, RTS ( bit 1 of HCR) CTS, Loopback RI input ( bit 2 of HCR) RI and IRQ enable ( bit 3 of HCR) DCD. Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way. Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit is internally connected to the modem control input DCD . Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected to the modem control input RI . Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS . Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . 3.2.4 Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins. 7 6 5 4 3 2 1 0 CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback mode. Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback mode. Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback mode. Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU. - 44 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read by the CPU. Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU. Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read. 3.2.5 UART FIFO Control Register (UFR) (Write only) This register is used to control the FIFO functions of the UART. 7 6 5 4 3 2 1 0 FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB) Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO. TABLE 3-3 FIFO TRIGGER LEVEL BIT 7 0 0 1 1 Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed. BIT 6 0 1 0 1 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 04 08 14 - 45 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY - 46 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 3.2.6 Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits. 7 6 5 0 4 0 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled 3 2 1 0 Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logic 0. Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-out interrupt is pending. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical 0. TABLE 3-4 INTERRUPT CONTROL FUNCTION ISR Bit 3 0 0 Bit 2 0 1 Bit 1 0 1 Bit 0 1 0 Interrupt priority First Interrupt Type INTERRUPT SET AND FUNCTION Interrupt Source Clear Interrupt UART Receive Status RBR Data Ready No Interrupt pending 1. OER = 1 2. PBER =1 Read USR - 3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 0 1 0 0 Second 1 1 0 0 Second FIFO Data Timeout Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty 0 0 1 0 Third TBR Empty 1. Write data into TBR 2. Read ISR (if priority is third) 0 0 0 0 Fourth Handshake status 1. TCTS = 1 3. FERI = 1 2. TDSR = 1 4. TDCD = 1 Read HSR ** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1. - 47 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 3.2.7 Interrupt Control Register (ICR) (Read/Write) This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1. 7 0 6 0 5 0 4 0 RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) 3 2 1 0 Bit 7-4: These four bits are always logic 0. Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt. 3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to 16 generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table in the next page illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps. - 48 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 3.2.9 User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. TABLE 3-5 BAUD RATE TABLE Pre-Div: 13 1.8461M Hz 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div:1.625 Pre-Div: 1.0 Decimal divisor used Error Percentage between to generate 16X clock desired and actual 14.769M Hz 24M Hz 400 650 2304 ** 600 880 1076 1200 2400 4800 9600 14400 16000 19200 28800 38400 57600 76800 153600 307200 460800 921600 975 1430 1478.5 1950 3900 7800 15600 23400 26000 31200 46800 62400 93600 124800 249600 499200 748800 1497600 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** ** ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B. - 49 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 4. INFRARED (IR) PORT The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless communication which can operate under various transmission protocols including IrDA 1.0 SIR, SHARP ASK-IR. IR port shares the same port with UART B port in W83977TF. Please refer to section 11.5 for configuration information. 5. PARALLEL PORT 5.1 Printer Interface Logic The parallel port of the W83977TF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83977TF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation. Table 5-1 shows the pin definitions for different modes of the parallel port. TABLE 5-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 Notes: n - 49 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY TABLE 5-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN NUMBER OF W83977TF 36 31 30 29 28 27 26 24 23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE O I/O I/O I/O I/O I/O I/O I/O I/O I I I I O I O O SPP nSTB PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nAFD nERR nINIT nSLIN PIN ATTRIBUTE --I I I I I --OD OD OD OD OD OD OD OD OD OD EXT2FDD --INDEX 2 PIN ATTRIBUTE --I I I I I ------OD OD OD OD OD OD OD OD EXTFDD --INDEX 2 TRAK02 WP2 RDATA2 DSKCHG2 --MOA 2 TRAK02 WP2 RDATA2 DSKCHG2 ------- DSA2 DSB2 MOB2 WD2 WE2 RWC2 HEAD2 DIR2 STEP 2 DSB2 MOB2 WD2 WE2 RWC2 HEAD2 DIR2 STEP 2 5.2 Enhanced Parallel Port (EPP) TABLE 5-2 PRINTER MODE AND EPP REGISTER ADDRESS A2 0 0 0 0 0 1 1 1 1 Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode. A1 0 0 1 1 1 0 0 1 1 A0 0 1 0 0 1 0 1 0 1 REGISTER Data port (R/W) Printer status buffer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/W) NOTE 1 1 1 1 2 2 2 2 2 - 50 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.2.1 Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper. 5.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows: 7 6 5 4 3 2 1 1 1 TMOUT ERROR SLCT PE ACK BUSY 0 Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. When this signal is active, the printer is busy and cannot accept data. Bit 6: This bit represents the current state of the printer's ACK signal. A 0 means the printer has received a character and is ready to accept another. Normally, this signal will be active for approximately 5 microseconds before BUSY stops. Bit 5: Logical 1 means the printer has detected the end of paper. Bit 4: Logical 1 means the printer is selected. Bit 3: Logical 0 means the printer has encountered an error condition. Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register. Bit 0: This bit is valid in EPP mode only. It indicates that a 10 S time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect. - 51 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows: 7 1 6 1 STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR 5 4 3 2 1 0 Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. Bit 4: A 1 in this position allows an interrupt to occur when ACK changes from low to high. Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. 5.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows: 7 6 5 4 3 2 1 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 - 52 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW causes an EPP address write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR causes an EPP address read cycle to be performed and the data to be output to the host CPU. 5.2.5 EPP Data Port 0-3 These four registers are available only in EPP mode. Bit definitions of each data port are as follows: 7 6 5 4 3 2 1 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (noninverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes an EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read cycle to be performed and the data to be output to the host CPU. 5.2.6 Bit Map of Parallel Port and EPP Registers REGISTER Data Port (R/W) Status Buffer (Read) Control Swapper (Read) Control Latch (Write) EPP Address Port R/W) EPP Data Port 0 (R/W) EPP Data Port 1 (R/W) 7 PD7 6 PD6 5 PD 5 PE 1 DIR PD 5 PD 5 PD 5 4 PD4 SLCT IRQEN IRQ PD4 PD4 PD4 3 PD3 2 PD2 1 1 PD1 1 0 PD0 TMOUT BUSY 1 1 PD7 PD7 PD7 ACK 1 1 PD6 PD6 PD6 ERROR SLIN SLIN PD3 PD3 PD3 INIT INIT PD2 PD2 PD2 AUTOFD AUTOFD PD1 PD1 PD1 STROBE STROBE PD0 PD0 PD0 - 53 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY EPP Data Port 2 (R/W) EPP Data Port 3 (R/W) PD7 PD7 PD6 PD6 PD 5 PD 5 PD4 PD4 PD3 PD3 PD2 PD2 PD1 PD1 PD0 PD0 - 54 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.2.7 EPP Pin Descriptions EPP NAME nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInits nAStrb TYPE O I/O I I I I O I O O EPP DESCRIPTION Denotes an address or data read or write operation. Bi-directional EPP address and data bus. Used by peripheral device to interrupt the host. Inactive to acknowledge that data transfer is completed. Active to indicate that the device is ready for the next transfer. Paper end; same as SPP mode. Printer selected status; same as SPP mode. This signal is active low. It denotes a data read or write operation. Error; same as SPP mode. This signal is active low. When it is active, the EPP device is reset to its initial operating mode. This signal is active low. It denotes an address read or write operation. 5.2.8 EPP Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port. A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 S have elapsed from the start of the EPP cycle to the time WAIT is deasserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0. 5.2.8.1 EPP Operation The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously. 5.2.8.2 EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high. b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above. 5.2.8.3 EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. - 55 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.3 Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions. Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. 5.3.1 ECP Register and Mode Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr ADDRESS Base+000h Base+000h Base+001h Base+002h Base+400h Base+400h Base+400h Base+400h Base+401h Base+402h I/O R/W R/W R R/W R/W R/W R/W R R/W R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register Note: The base addresses are specified by CR60 and 61, which are determined by configuration register or hardware setting. MODE 000 001 010 011 100 101 110 111 SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode DESCRIPTION EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode) Reserved Test mode Configuration mode Note: The mode selection bits are bit 7-5 of the Extended Control Register. - 56 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows: 7 6 5 4 3 2 1 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows: 7 6 5 4 3 2 1 0 Address or RLE Address/RLE 5.3.3 Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows: 7 6 5 4 3 2 1 1 1 0 1 nFault Select PError nAck nBusy - 57 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read. 5.3.4 Device Control Register (DCR) The bit definitions are as follows: 7 1 6 1 strobe autofd nInit SelectIn ackIntEn Direction 5 4 3 2 1 0 Bit 6, 7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode. Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the CPU due to a low to high transition on the ACK input. Bit 3: This bit is inverted and output to the SLIN output. 0 The printer is not selected. 1 The printer is selected. Bit 2: This bit is output to the INIT output. Bit 1: This bit is inverted and output to the AFD output. Bit 0: This bit is inverted and output to the STB output. - 58 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. 5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 5.3.7 tFifo (Test FIFO Mode) Mode = 110 Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines. 5.3.8 cnfgA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation. 5.3.9 cnfgB (Configuration Register B) Mode = 111 The bit definitions are as follows: 7 6 5 4 3 2 1 1 1 0 1 IRQx 0 IRQx 1 IRQx 2 intrValue compress Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. - 59 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 5-3: Reflect the IRQ resource assigned for ECP port. cnfgB[5:3] 000 001 010 011 100 101 110 111 IRQ resource reflect other IRQ resources selected by PnP register (default) IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written. 5.3.10 ecr (Extended Control Register) Mode = all 7 6 5 4 3 2 1 0 This register controls the extended ECP parallel port functions. The bit definitions are follows: empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Bit 7-5: These bits are read/write and select the mode. 000 001 Standard Parallel Port mode. The FIFO is reset in this mode. PS/2 Parallel Port mode. This is the same as 000 except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0. ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. Reserved. Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. 010 011 100 101 110 111 - 60 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally. Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt. (a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be read from the FIFO. Bit 1: Read only 0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full. Bit 0: Read only 0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty. 5.3.11 Bit Map of ECP Port Registers D7 data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr PD7 Addr/RLE nBusy 1 D6 PD6 D5 PD5 D4 PD4 D3 PD3 D2 PD2 D1 PD1 D0 PD0 NOTE 2 Address or RLE field nAck 1 PError Directio Select ackIntEn nFault SelectIn 1 nInit 1 autofd 1 strobe 1 1 2 2 2 Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 compress 0 intrValue MODE 0 1 1 1 nErrIntrEn 0 1 dmaEn 0 1 serviceIntr 0 1 full 0 1 empty Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. - 61 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.3.12 ECP Pin Descriptions NAME nStrobe (HostClk) TYPE O DESCRIPTION The nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes with Busy. These signals contains address or data or RLE data. This signal indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. It indicates whether the data lines contain ECP command information or data in the reverse direction. When in reverse direction, normal data are transferred when Busy (PeriphAck) is high and an 8-bit command is transferred when it is low. This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when it is asserted. This signal indicates whether the data lines contain ECP address or data in the forward direction. When in forward direction, normal data are transferred when nAutoFd (HostAck) is high and an 8-bit command is transferred when it is low. Generates an error interrupt when it is asserted. This signal is valid only in the forward direction. The peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. PD<7:0> nAck (PeriphClk) Busy (PeriphAck) I/O I I PError (nAckReverse) I Select (Xflag) nAutoFd (HostAck) I O nFault (nPeriphRequest) I nInit (nReverseRequest) O nSelectIn (ECPMode) O - 62 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required: (a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. 5.3.13.1 Mode Switching Software will execute P1284 negotiation and all operations prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010). If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can be changed only in mode 001. When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. 5.3.13.2 Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. 5.3.13.3 Data Compression The W83977TF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. 5.3.14 FIFO Operation The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled. - 63 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 5.3.15 DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA. 5.3.16 Programmed I/O (NON-DMA) Mode The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. 5.4 Extension FDD Mode (EXTFDD) In this mode, the W83977TF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOB and DSB will be forced to inactive state. (2) Pins DSKCHG , RDATA , WP, TRAK0, INDEX will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. 5.5 Extension 2FDD Mode (EXT2FDD) In this mode, the W83977TF changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table5-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOA , DSA , MOB , and DSB will be forced to inactive state. (2) Pins DSKCHG, RDATA , WP, TRAK0, and INDEX will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. - 64 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 6. KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977TF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM(R)compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. Then, the controller will assert an interrupt to the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge is received for the previous data byte. P24 P25 P21 KINH P17 P20 P27 KIRQ MIRQ GATEA20 KBRST KDAT KCLK 8042 GP I/O PINS Multiplex I/O PINS P10 P26 T0 P12~P16 P23 T1 P22 P11 MCLK MDAT Keyboard and Mouse Interface 6.1 Output Buffer The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer can only be read when the output buffer full bit in the register is "1". 6.2 Input Buffer The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is 0 . - 65 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 6.3 Status Register The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT 0 1 2 BIT FUNCTION Output Buffer Full Input Buffer Full System Flag DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) 3 4 5 6 7 Command/Data Inhibit Switch Auxiliary Device Output Buffer General Purpose Timeout Parity Error 6.4 Commands COMMAND 20h 60h FUNCTION Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller BIT 7 6 5 4 3 2 1 0 Reserved IBM Keyboard Translate Mode Disable Auxiliary Device Disable Keyboard Reserve System Flag Enable Auxiliary Interrupt Enable Keyboard Interrupt BIT DEFINITION A4h Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded - 66 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 6.4 Commands, continued COMMAND A5h A6h A7h A8h A9h FUNCTION Load Password Load Password until a "0" is received from the system Enable Password Enable the checking of keystrokes for a match with the password Disable Auxiliary Device Interface Enable Auxiliary Device Interface Interface Test BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high Auxiliary Device "Data" line is stuck low Auxiliary Device "Data" line is stuck low AAh ABh Self-test Returns 055h if self test succeeds Interface Test BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Keyboard "Clock" line is stuck low Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low Keyboard "Data" line is stuck high ADh AEh C0h C1h C2h D0h D1h D2h D3h D4h E0h FXh Disable Keyboard Interface Enable Keyboard Interface Read Input Port(P1) and send data to the system Continuously puts the lower four bits of Port1 into STATUS register Continuously puts the upper four bits of Port1 into STATUS register Send Port2 value to the system Only set/reset GateA20 line based on the system data bit 1 Send data back to the system as if it came from Keyboard Send data back to the system as if it came from Auxiliary Device Output next received byte of data from system to Auxiliary Device Reports the status of the test inputs Pulse only RC(the reset line) low for 6S if Command byte is even - 67 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 6.5 Hardware GATEA20/Keyboard Reset Control Logic The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows: 6.5.1 KB Control Register (Logic Device 5, CR-F0) BIT NAME 7 KCLKS1 6 5 4 3 2 P92EN 1 HGA20 0 HKBRST KCLKS0 Reserved Reserved Reserved KCLKS1, KCLKS0 This 2 bits are for the KBC clock rate selection. = 0 0 KBC clock input is 6 Mhz = 0 1 KBC clock input is 8 Mhz = 1 0 KBC clock input is 12 Mhz = 1 1 KBC clock input is 16 Mhz P92EN (Port 92 Enable) A "1" on this bit enables Port 92 to control GATEA20 and KBRESET. A "0" on this bit disables Port 92 functions. HGA20 (Hardware GATE A20) A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal. A "0" on this bit disables hardware GATEA20 control logic function. HKBRST (Hardware Keyboard Reset) A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal. A "0" on this bit disables hardware KB RESET control logic function. When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the KBRESET is pulse low for 6S(Min.) with 14S(Min.) delay. GATEA20 and KBRESET are controlled by either the software control or the hardware control logic and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 when P92EN bit is set. 6.5.2 Port 92 Control Register (Default Value = 0x24) BIT NAME 7 Res. (0) 6 Res. (0) 5 Res. (1) 4 Res. (0) 3 Res. (0) 2 Res. (1) 1 SGA20 0 PLKBRST SGA20 (Special GATE A20 Control) A "1" on this bit drives GATE A20 signal to high. A "0" on this bit drives GATE A20 signal to low. PLKBRST (Pull-Low KBRESET) A "1" on this bit causes KBRESET to drive low for 6S(Min.) with 14S(Min.) delay. Before issuing another keyboard reset command, the bit must be cleared. - 68 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 6.6 OnNow / Security Keyboard and Mouse Wake-Up ---- Programmable Keyboard / Mouse Wake-Up Functions Winbond's unique programmable keyboard/ mouse wake-up functions provide the system diversified methods for either OnNow wake-up application, or security control application. The keyboard or mouse can wake up the system by producing a panel switch low pulse on PANSWOUT pin, and connect TM it to chipset (for example Intel chipset TX, LX PIIX4) panel switch input. The wake-up conditions can be programmed as pre-determined or any keys/buttons. To implement this function, a 32.768KHz crystal must be installed between XTAL1 and XTAL2, or a 32.768KHz clock to be connected to XTAL1 and leave XTAL2 open. The VSB pin must be connected to +5V VSB of ATX power supply, and an external battery should be installed on VBAT pin to store the data (the passwords and wake-up status which had been set already) when power fails. 6.6.1 Keyboard Wake-Up Function The keyboard wake-up function is enable by setting LD-0A CR-E0 bit 6. The pre-determined keys data are stored in registers, and they can be access by an indirection method. At first, write their index address to LD-0A CR-E1, then access them by reading/writing LD-0A CR-E2. A zero data is written to the register means the comparison of this register will be ignored. The pre-programmed keys may be 1 to 5 keys with various combinations. If LD-0A CR-E0 bit 0 is set, the system will be waken up after any key struck. 6.6.2 Keyboard Password Wake-Up Function To implement this function, the bit 7 of LD-0A CR-E0 must be set, and panel switch input is connected to PANSWIN pin. Thus PANSWIN is blocked to PANSWOUT , by setting LD-0A CR-E0 properly and make only keyboard can wake up the system with preset keys (password). 6.6.3 Mouse Wake-Up Function The mouse wake-up function is activated by setting bit 5 of LD-0A CR-E0. If bit 1 of LD-0A CR-E0 is set, any movement or button clicking will make up the system. Otherwise, the mouse can wake up the system only by clicking its button twice successively with the mouse unmoved. The bit 4 of LD0A CR-E0 determines which button (left or right) to perform wake-up function. - 69 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 7. GENERAL PURPOSE I/O W83977TF provides 23 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 23 GP I/O ports are divided into three groups, the first group contains 8 ports, the second group contains only 7 ports, and the third group contains 8 ports. Each port in first group corresponds to a configuration register in logical device 7, the second group in logical device 8, and the third group in logical device 9. Users can select those I/O ports functions by independently programming those configuration registers. Figure 7.1, 7.2, and 7.3 respectively show the GP I/O port's structure of logical device 7, 8, and 9. Right after Power-on reset, those ports default to perform basic I/O functions. Figure 7.1 -69 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY Figure 7.2 Figure 7.3 -70 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 7.1 Basic I/O functions The Basic I/O functions of W83977TF provide several I/O operations including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available in the second group of the GP I/O port). Common Interrupt is the ORed function of all interrupt channels in the second group of the GP I/O ports, and it also connects to a 1ms debounce filter which can reject a noise of 1 ms pulse width or less. There are three 8-bit registers (GP1, GP2, and GP3) which are directly connected to those GP I/O ports. Each GP I/O port is represented as a bit in one of three 8-bit registers. Only 6 bits of GP2 are implemented. Table 7.1.1 shows their combinations of Basic I/O functions, and Table 7.1.2 shows the register bit assignments of GP1, GP2, and GP3. Table 7.1.1 I/O BIT 0 = OUTPUT 1 = INPUT 0 0 0 0 1 1 1 1 ENABLE INT BIT 0 = DISABLE 1 = ENABLE 0 0 1 1 0 0 1 1 POLARITY BIT 0 = NON INVERT 1 = INVERT 0 1 0 1 0 1 0 1 Basic non-inverting output Basic inverting output Non-inverted output bit value of GP2 drive to Common Interrupt Inverted output bit value of GP2 drive to Common Interrupt Basic non-inverting input Basic inverting input Non-inverted input drive to Common Interrupt Inverted input drive to Common Interrupt BASIC I/O OPERATIONS -71 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY Table 7.1.2 GP I/O PORT ACCESSED REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP1 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP2 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 0 BIT 1 BIT 2 BIT 3 GP3 BIT 4 BIT 5 BIT 6 BIT 7 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 -72 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 7.2 Alternate I/O Functions W83977TF provides several alternate functions which are scattered among the GP I/O ports. Table 7.2.1 shows their assignments. Polarity bit can also be set to alter their polarity. Table 7.2.1 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP30 GP31 GP32 GP33 GP34 ALTERNATE FUNCTION Interrupt Steering Interrupt Steering Watch Dog Timer Output/IRRX input Power LED output/IRTX output General Purpose Address Decoder/Keyboard Inhibit(P17) General Purpose Write Strobe/ 8042 P12 Watch Dog Timer Output Power LED output Keyboard Reset (8042 P20) 8042 P13 8042 P14 8042 P15 8042 P16 GATE A20 (8042 P21) Interrupt Steering Interrupt Steering General Purpose Address Decoder General Purpose Address Decoder Watch Dog Timer Output 7.2.1 Interrupt Steering GP10, GP11, GP30, and GP31 can be programmed to map their own interrupt channels. The selection of IRQ channel can be done in configuration registers CR70 and CR72 of logical device 7 and logical device 9. Each interrupt channel also has its own 1 ms debounce filter that is used to reject any noise whose width is equal to or less than 1 ms. -73 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 7.2.2 Watch Dog Timer Output Watch Dog Timer contains a one minute resolution down counter, CRF2 of Logical Device 8, and two watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down counter can be programmed within the range from 1 to 255 minutes. Writing any new non-zero value to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also contains nonzero value) will cause the Watch Dog Timer to reload and start to count down from the new value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1. 7.2.3 Power LED The Power LED function provides 1 Hertz rate toggle pulse output with 50 percent duty cycle. Table 7.2.2 shows how to enable Power LED. Table 7.2.2 WDT_CTRL1 BIT[1] 1 0 0 0 WDT_CTRL0 BIT[3] X 0 1 1 WDT_CTRL1 BIT[0] X X 0 1 POWER LED STATE 1 Hertz Toggle pulse Continuous high or low * Continuous high or low * 1 Hertz Toggle pulse * Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configuration registers. 7.2.4 General Purpose Address Decoder General Purpose Address Decoder provides two address decode as AEN equal to logic 0. The address base is stored at CR62, CR63 of logical device 7 for GP14 and at CR62-65 of logical device 9 for GP32 and GP33. The decoding output is normally active low. Users can alter its polarity through the polarity bit of the GP14, GP32, and GP33's configuration register. 7.2.5 General Purpose Write Strobe General Purpose Write Strobe is an address decoder that performs like General Purpose Address Decoder, but it has to be qualified by IOW and AEN. Its output is normally active low. Users can alter its polarity through the polarity bit of the GP15's configuration register. -74 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 8. PLUG AND PLAY CONFIGURATION The W83977TF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83977TF, there are nine Logical Devices (from Logical Device 0 to Logical Device A with the exception of logical device 4 and 6 for compatibility) which correspond to nine individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), GPIO1 (logical device 7), GPIO2 (logical device 8), GPIO3 (logical device 9), and ACPI ((logical device A). Each Logical Device has its own configuration registers (above CR30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7. 8.1 Compatible PnP 8.1.1 Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows: HEFRAS 0 1 address and value write 87h to the location 3F0h twice write 87h to the location 370h twice -75 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY After Power-on reset, the value on RTSA (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 3F0h or 370h). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 3F0h or 370h same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 3F1h or 371h). After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 8.1.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83977TF enters the default operating mode. Before the W83977TF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 3F0h or 370h (as described in previous section). 8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h (as described in section 8.1.1) on PC/AT systems; the EFDRs are read/write registers with port address 3F1h or 371h (as described in section 8.1.1) on PC/AT systems. -76 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9. ACPI REGISTERS FEATURES W83977TF supports both ACPI and legacy power managements. The switch logic of the power managment block generates an SMI interrupt in the legacy mode and an SCI interrupt in the ACPI mode. For the legacy mode, the SMI_EN bit is used. If it is set, it routes the power management events to the SMI interrupt logic. For the ACPI mode, the SCI_EN bit is used. If it is set, it route the power management events to the SCI interrupt logic. The SMI_EN bit is located in the configuration register block of Device A and the SCI_EN bit is located in the PM1 register block. See the following figure for illustration. SMI_EN IRQs from SCI to SMI IRQs SMI Logic 0 1 SMI output Logic SMI PM Timer SCI_EN from SMI to SCI Bus Master SCI SCI output Logic SCI Logic IRQs SCI WAK_STS Device Idle Timers Device Trap Global STBY Timer Sleep/Wake State machine Clock Control The SMI interrupt is routed to pin SMI , which is dedicated for the SMI interrupt output. Another way to output the SMI interrupt is to route to pin IRQSER, which is the signal pin in the Serial IRQ mode. The SCI interrupt can be routed to pin SCI , which is dedicated for the SCI function. Or it can be routed to one interrupt request pin, which is selected through CR70.bit3 - 0 of logical device 9. Another way is to output the SCI interrupt to pin IRQSER if serial IRQ mode is enabled. -77 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9.1 SMI to SCI/SCI to SMI and Bus Master The following figure illustrates the process of generating an interrupt from SMI to SCI or from SCI to SMI . clear from SMI to SCI BIOS_RLS GBL_EN clear from SCI to SMI GBL_RLS BIOS_EN clear BUS Master SCI BM_CNTPL BM_RLD set set set GBL_STS To SCI Logic BIOS_STS To SMI Logic BM_STS To SCI Logic : Status bit : Enable bit For the BIOS software to raise an event to the ACPI software, BIOS_RLS, GBL_EN, and GBL_STS bits are involved. GBL_EN is the enable bit and the GBL_STS is the status bit. Both are controlled by the ACPI software. If BIOS_RLS is set by the BIOS software and GBL_EN is set by the ACPI software, an SCI interrupt is raised. Writing a 1 to BIOS_RLS sets it to logic 1 and also sets GBL_STS to logic 1. Writing a 0 to BIOS_RLS has no effect. Wrinting a 1 to GBL_STS clears it to logic 0 and also clears BIOS_RLS to logic 0. Writing a 0 to GBL_STS has no effect. -78 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY For the ACPI software to raise an event to the BIOS software, GBL_RLS, BIOS_EN, and BIOS_STS bits are involved. BIOS_EN is the enable bit and the BIOS_STS is the status bit. Both are controlled by the BIOS software. If GBL_RLS is set by the ACPI software and BIOS_EN is set by the BIOS software, an SMI is raised. Writing a 1 to GBL_RLS sets it to logic 1 and also sets BIOS_STS to logic 1. Writing a 0 to GBL_RLS has no effect. Wrinting a 1 to BIOS_STS clears it to logic 0 and also clears GBL_RLS to logic 0. Writing a 0 to BIOS_STS has no effect. For the bus master to raise an event to the ACPI software, BM_CNTRL, BM_RLD, and BM_STS bits are involved. Both BM_RLD and BM_STS are controlled by the ACPI software. If BM_CNTRL is set by the BIOS software and BM_RLD is set by the ACPI software, an SCI interrupt is raised. Writing a 1 to BM_CNTRL sets it to logic 1 and also sets BM_STS to logic 1. Writing a 0 to BM_CNTRL has no effect. Wrinting a 1 to BM_STS clears it to logic 0 and also clears BM_CNTRL to logic 0. Writing a 0 to BM_STS has no effect. 9.2 Power Management Timer In the ACPI specification, it requires a power management timer. The power management timer is a 24-bit fixed rate free running up-count timer that runs off a 3.579545MHZ clock. The power management timer corresponds to status bit (TMR_STS) and enable bit (TMR_EN). The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Three registers are used to read the timer value which are located in the PM1 register block. The power management timer has one enabel bit (TMR_ON) to turn ii on or off. The TMR_ON is located in GPE register block. If it is cleared to 0, the power management timer function would not work. There are no timer reset requirements, except that the timer should function after power-up. See the following figure for illustration. TMR_ON 3.579545 MHz 24 bit counter Bits (23-0) 24 TMR_STS To SCI Logic TMR_EN TMR_VAL -79 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9.3 ACPI Registers (ACPIRs) The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A register block may be a event register block which deals with ACPI events or a control register block which deals with control features. The order in the event register block is a status register followed by an enable register. Each event register, if implemented, contains two two register: a status register and an enable register, of 16 bits wide each. The status register indicates which event triggers the ACPI System Control Interrupt ( SCI ). When the hardware event occurs, the corresponding status bit will be set. However, the corresponding enable bit is also required to be set before an SCI interrupt could be raised. If the enable bit is not set, the software can examine the state of the hardware event by reading the status bit without generating an SCI interrupt. Any status bit, unless otherwise noted, can only be set by specific hardware event. It is cleared by writing a 1 to its bit position and writing a 0 has no effect. Except some special status bits, every status bit has the corresponding enable bit on the same bit position in the enable register. Those status bits which have no corresponding enable bit are read for special purpose. Reverved or unimplemented enable bits always return zero, and writing to these bits should has no effect. The control bit in the control register provides some special control function over the hardware event, or some special control over SCI event. Reserved or unimplemented control bits always return zero, and writing to those bits should has no effect. Table 9-1 (sec. 9.3.21) lists the PM1 register block and its registers. The base address of PM1 register block is named as PM1a_EVT_BLK in the ACPI specification and is specified in CR60, 61 of logical device A. Table 9-2 (sec. 9.3.21) lists the GPE register block and its registers. The base address of generalpurpose event block GPE0 is named as GPE0_BLK in the ACPI specification and is specified in CR62, 63 of logical device A. The base address of general-purpose event block GPE1 is named as GPE1_BLK in the ACPI specification and is specified in CR64, 65 of logical device A. 9.3.1 Power Management 1 Status Register 1 (PM1STS1) Register Location: Default Value: Attribute: Size: 8 bits 7 6 5 4 3 2 1 0 TMR_STS Reserved Reserved Reserved BM_STS GBL_STS Reserved Reserved -80 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 0 Name TMR_STS Description This bit is the timer carry status bit. This bit is set anytime the bit 23 of the 24-bit counter changes (whenever the MSB changes from low to high or high to low). When TMR_EN and TMR_STS are set, a power magement event is raised. This bit is only set by hardware and can only be cleared by writing a 1 to this bit position. Writing a 0 has no effect. Reserved. This is the bus master status bit. Writing a 1 to BM_CNTRL also sets BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a 0 has no effect. This is the global status bit. This bit is set when the BIOS wants the attention of the SCI handler. BIOS sets this bit by setting BIOS_RLS and can only be cleared by writing a 1 to this bit position. Writing a 1 to this bit position also clears BIOS_RLS. Writing a 0 has no effect. Reserved. These bits always return zeros. 1-3 4 Reserved BM_STS 5 GBL_STS 6-7 Reserved 9.3.2 Power Management 1 Status Register 2 (PM1STS2) Register Location: Default Value: Attribute: Size: 7 8 bits 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved WAK_STS Bit 0-6 7 Name Reserved WAK_STS Reserved. Description This bit is set when the system is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. Writing a 0 has no effect. When the WAK_STS is cleared and all devices are in sleeping state, the whole chip enters the sleeping state. -81 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9.3.3 Power Management 1 Enable Register 1(PM1EN1) Register Location: Default Value: Attribute: Size: 8 bits 7 6 5 4 3 2 1 0 TMR_EN Reserved Reserved Reserved GBL_EN Reserved Reserved Reserved Bit 0 Name TMR_EN Description This is the timer carry interrupt enable bit. When this bit is set then an SCI event is generated whenever the TMR_STS bit is set. When this bit is reset then no interrupt is generated even when the TMR_STS bit is set. Reserved. These bits always return a value of zero. The global enable bit. When both the GBL_EN bit and the GBL_STS bit are set, an SCI interrupt is raised. Reserved. 1-4 5 6-7 Reserved GBL_EN Reserved 9.3.4 Power Management 1 Enable Register 2 (PM1EN2) Register Location: Default Value: Attribute: Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0-7 Name Reserved Description Reserved. These bits always return zeros. -82 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9.3.5 Power Management 1 Control Register 1 (PM1CTL1) Register Location: Default Value: Attribute: Size: 8 bits 7 6 5 4 3 2 1 0 SCI_EN BM_RLD GBL_RLD Reserved Reserved Reserved Reserved Reserved Bit 0 Name SCI_EN Description Select whether the power management event triggers an SCI or an SMI interrupt. When this bit is set, then the power management events will generate an SCI interrupt. When this bit is reset and SMI_EN bit is set, then the power management events will generate an SMI interrupt. This is the bus master reload enable bit. If this bit is set and BM_CNTRL is set, an SCI interrupt is raised. The global release bit. This bit is used by the ACPI software to raise an event to the BIOS software. The BIOS software has a corresponding enable and status bit to control its ability to receive the ACPI event. Setting GBL_RLS sets BIOS_STS, and it generates an SMI interrupt if BIOS_EN is also set. Reserved. These bits always return zeros. 1 2 BM_RLD GBL_RLS 3-7 Reserved 9.3.6 Power Management 1 Control Register 2 (PM1CTL2) Register Location: Default Value: Attribute: Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0-7 Name Reserved Description Reserved. These bits always return zeros. -83 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9.3.7 Power Management 1 Control Register 3 (PM1CTL3) Register Location: Default Value: Attribute: Size: 7 8 bits 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0-7 Name Reserved Description Reserved. These bits always return zeros. 9.3.8 Power Management 1 Control Register 4 (PM1CTL4) Register Location: Default Value: Attribute: Size: 7 8 bits 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0-7 Name Reserved Description Reserved. These bits always return zeros. -84 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9.3.9 Power Management 1 Timer 1 (PM1TMR1) Register Location: Default Value: Attribute: Size: 7 8 bits 6 5 4 3 2 1 0 TMR_VAL0 TMR_VAL1 TMR_VAL2 TMR_VAL3 TMR_VAL4 TMR_VAL5 TMR_VAL6 TMR_VAL7 Bit 0-7 Name TMR_VAL Description This read-only field returns the running count of the power management timer. This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in the working state. The timer is reset and then continues counting until the CLKIN input the the chip is stopped. If the clock is restarted without a MR reset, then the counter will resume counting from where it stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. 9.3.10 Power Management 1 Timer 2 (PM1TMR2) 7 6 5 4 3 2 1 0 Register Location: Default Value: Attribute: Size: TMR_VAL8 TMR_VAL9 TMR_VAL10 TMR_VAL11 TMR_VAL12 TMR_VAL13 TMR_VAL14 TMR_VAL15 -85 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 0-7 Name TMR_VAL Description This read-only field returns the running count of the power management timer. This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in the working state. The timer is reset and then continues counting until the CLKIN input the the chip is stopped. If the clock is restarted without a MR reset, then the counter will resume counting from where it stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. 9.3.11 Power Management 1 Timer 3 (PM1TMR3) 7 6 5 4 3 2 1 0 Register Location: Default Value: Attribute: Size: TMR_VAL16 TMR_VAL17 TMR_VAL18 TMR_VAL19 TMR_VAL20 TMR_VAL21 TMR_VAL22 TMR_VAL23 Bit 0-7 Name TMR_VAL Description This read-only field returns the running count of the power management timer. This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in the working state. The timer is reset and then continues counting until the CLKIN input the the chip is stopped. If the clock is restarted without a MR reset, then the counter will resume counting from where it stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. -86 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9.3.12 Power Management 1 Timer 4 (PM1TMR4) 7 6 5 4 3 2 1 0 Register Location: Default Value: Attribute: Size: Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0-7 Name Reserved Description Reserved. These bits always return zeros. 9.3.13 General Purpose Event 0 Status Register 1 (GP0STS1) 7 6 5 4 3 2 1 0 Register Location: Default Value: Attribute: Size: URBSCISTS URASCISTS FDCSCISTS PRTSCISTS KBCSCISTS MOUSCISTS Reserved Reserved These bits indicate the status of the SCI input, which is set when the device's IRQ is raised. If the corresponding enable bit in the SCI interrupt enable register (in GP0EN1) is set, an SCI interrupt is raised and routed to the output pin. Wrinting a 1 clears the bit, and wrinting a 0 has no effect. If the bit is not cleared, new IRQ to the SCI logic input is ignored and no SCI interrupt will be raised. -87 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 0 1 2 3 4 5 6-7 Name URBSCISTS URASCISTS FDCSCISTS PRTSCISTS KBCSCISTS MOUSCISTS Reserved Description UART B SCI status, which is set by the UART B IRQ. UART A SCI status, which is set by the UART A IRQ. FDC SCI status, which is set by the FDC IRQ. PRT SCI status, which is set by the printer port IRQ. KBC SCI status, which is set by the KBC IRQ. MOUSE SCI status, which is set by the MOUSE IRQ. Reserved. 9.3.14 General Purpose Event 0 Status Register 2 (GP0STS2) 7 6 5 4 3 2 1 0 Register Location: Default Value: Attribute: Size: Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0-7 Name Reserved Description Reserved. These bits always return zeros. -88 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 9.3.15 General Purpose Event 0 Enable Register 1 (GP0EN1) Register Location: 7 6 5 4 3 2 1 0 URBSCIEN URASCIEN FDCSCIEN PRTSCIEN KBCSCIEN MOUSCIEN Reserved Reserved These bits are used to enable the device's IRQ sources into the SCI logic. The SCI logic output for the IRQs is as follows: SCI logic output = (URBSCIEN and URBSCISTS) or (URASCIEN and URASCISTS) or (FDCSCIEN and FDCSCISTS) or (PRTSCIEN and PRTSCISTS) or (KBCSCIEN and KBCSCISTS) or (MOUSCIEN and MOUSCISTS) Bit 0 1 2 3 4 5 6-7 Name URBSCIEN URASCIEN FDCSCIEN PRTSCIEN KBCSCIEN MOUSCIEN Reserved Description UART B SCI enable, which controls the UART B IRQ. UART A SCI enable, which controls the UART A IRQ. FDC SCI enable, which controls the FDC IRQ. printer port SCI enable, which controls the printer port IRQ. KBC SCI enable, which controls the KBC IRQ. MOUSE SCI enable, which controls the MOUSE IRQ. Reserved. 9.3.16 General Purpose Event 0 Enable Register 2 (GP0EN2) Register Location: -89 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0-7 Name Reserved Description Reserved. These bits always return zeros. 9.3.17 General Purpose Event 1 Status Register 1 (GP1STS1) 7 6 5 4 3 2 1 0 Register Location: Default Value: Attribute: Size: BIOS_STS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0 Name BIOS_STS Description The BIOS status bit. This bit is set when GBL_RLS is set. If BIOS_EN is set, setting GBL_RLS will raise an SMI event. Writing a 1 to its bit location clears BIOS_STS and also clears GBL_RLS. Writing a 0 has no effect. Reserved. 1-7 Reserved 9.3.18 General Purpose Event 1 Status Register 2 (GP1STS2) Register Location: Default Value: Attribute: Size: 8 bits -90 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 0-7 Name Reserved Description Reserved. These bits always return zeros. 9.3.19 General Purpose Event 1 Enable Register 1 (GP1EN1) Register Location: 7 6 5 4 3 2 1 0 BIOS_EN TMR_ON Reserved Reserved Reserved Reserved Reserved Reserved Bit 0 Name BIOS_EN Description This bit is raise the SMI event. When this bit is set and the ACPI software writes a 1 to the GBL_RLS bit, an SMI event is raised on the SMI logic output. This bit is used to turn on the power management timer. 1 = timer on; 0 = timer off. Reserved. 1 2-7 TMR_ON Reserved 9.3.20 General Purpose Event 1 Enable Register 2 (GP1EN2) Register Location: -91 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 7 6 5 4 3 2 1 0 BIOS_RLS BM_CNTRL Reserved Reserved Reserved Reserved Reserved Reserved Bit 0 Name BIOS_RLS Description The BIOS release bit. This bit is used by the BIOS software to raise an event to the ACPI software. The ACPI software has a corresponding enable and status bit to control its ability to receive the ACPI event. Setting BIOS_RLS sets GBL_STS, and it generates an SCI interrupt if GBL_EN is also set. Writing a 1 to its bit position sets this bit and also sets the BM_STS bit. Writing a 0 has no effect. This bit is cleared by writing a 1 to the GBL_STS bit. This bit is used to set the BM_STS bit and if the BM_RLD bit is also set, then an SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also sets BM_STS. Writing a 0 has no effect. Wrinting a 1 to BM_STS clears BM_STS and also clears BM_CNTRL. Reserved. 1 BM_CNTRL 2-7 Reserved 9.3.21 Register Address Bit Map Configuration Registers Power-On Reset Value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Table 9-1: Bit Map of PM1 Register Block D7 D6 D5 D4 D3 D2 D1 D0 PM1STS1 PM1STS2 PM1EN1 PM1EN2 PM1CTL1 PM1CTL2 PM1CTL3 PM1CTL4 PM1TMR1 PM1TMR2 PM1TMR3 PM1TMR4 0 WAK_STS 0 0 0 0 0 0 TMR_VAL7 TMR_VAL15 TMR_VAL23 0 0 0 0 0 0 0 0 0 TMR_VAL6 TMR_VAL14 TMR_VAL22 0 GBL_STS 0 GBL_EN 0 0 0 0 0 TMR_VAL5 TMR_VAL13 TMR_VAL21 0 BM_STS 0 0 0 0 0 0 0 TMR_VAL4 TMR_VAL12 TMR_VAL20 0 0 0 0 0 0 0 0 0 TMR_VAL3 TMR_VAL11 TMR_VAL19 0 0 0 0 0 GBL_RLS 0 0 0 TMR_VAL2 TMR_VAL10 TMR_VAL18 0 0 0 0 BM_RLD 0 0 0 TMR_VAL1 TMR_VAL9 TMR_VAL17 0 TMR_STS 0 TMR_EN 0 SCI_EN 0 0 0 TMR_VAL0 TMR_VAL8 TMR_VAL16 0 -92 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY Table 9-2: Bit Map of GPE Register Block Register Address Power-On Reset Value GP0STS1 GP0STS2 GP0EN1 GP0EN2 GP1STS1 GP1STS2 GP1EN1 GP1EN2 D7 D6 D5 D4 D3 D2 D1 D0 10. SERIAL IRQ W83977TF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI System, Version 6.0. Timing Diagrams For IRQSER Cycle Start Frame timing with source sampled a low pulse on IRQ1 SL or H PCICLK IRQSER 1 START START FRAME H R T S IRQ0 FRAME R T IRQ1 FRAME S R T S IRQ2 FRAME R T Drive Source H=Host Control IRQ1 Host Controller SL=Slave Control R=Recovery None IRQ1 T=Turn-around None S=Sample 1. Start Frame pulse can be 4-8 clocks wide. -93 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY Stop Frame Timing with Host using 17 IRQSER sampling period IRQ14 FRAME S R T S IRQ15 FRAME R T S IOCHCK FRAME R T 2 I STOP FRAME H R T NEXT CYCLE PCICLK IRQSER 1 STOP 3 START Drive None H=Host Control IRQ15 R=Recovery None T=Turn-around Host Controller S=Sample I=Idle 1. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. 2. There may be none, one or more Idle states during the Stop Frame. 3. The next IRQSER cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stip Frame. 10.1 Start Frame There are two modes of operation for the IRQSER Start frame: Quiet mode and Continuous mode. In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and then tristates it. This brings all the states machines of the peripherals from idle to active states. The host controller will then take over driving IRQSER signal low in the next clock and will continue driving the IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4 to 8 clock periods. After these clocks, the host controller will drive the IRQSER high for one clock and then tri-states it. In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line information. The host controller drives the IRQSER signal low for 4 to 8 clock periods. Upon a reset, the IRQSER signal is defaulted to the Continuous mode for the host controller to initiate the first Start frame. 10.2 IRQ/Data Frame Once the start frame has been initiated, all the peripherals must start counting frames based on the rsing edge of the start pulse. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device left the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 10-1. 10.3 Stop Frame After all IRQ/Data Frames have completed, the host controller will terminate IRQSER by a Stop frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If the Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode. -94 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY Table 10-1 IRQSER Sampling periods IRQ/Data Frame 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 32:22 Signal Sampled IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK INTA INTB INTC INTD Unassigned # of clocks past Start 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 95 10.4 Reset and Initialization After MR reset, IRQSER Slaves are put into the Continuous(Idle) mode. The Host Controller is responsible for starting the initial IRQSER Cycle to collect system's IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent IRQSER cycles. It's the Host Controller's responsibility to provide the default values to 8259's and other system logic before the first IRQSER cycle is performed. For IRQSER system suspend, insertion, or removal application, the Host controller should be programmed into Continuous(Idle) mode first. This is to guarantee IRQSER bus in the Idle state before the system configuration changes. -95 - Publication Release Date:March 1998 Revision 0.62 W83977TF PRELIMINARY 11. CONFIGURATION REGISTER 11.1 Chip (Global) Control Register CR02 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: SWRST --> Soft Reset. CR07 Bit 7 - 0: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x97 (read only). CR21 Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x73 (read only). CR22 (Default 0xff) Bit 7 - 6: Reserved. Bit 5: URBPWD = 0 Power down = 1 No Power down Bit 4: URAPWD = 0 Power down = 1 No Power down Bit 3: PRTPWD = 0 Power down = 1 No Power down Bit 2, 1: Reserved. Bit 0: FDCPWD = 0 Power down = 1 No Power down CR23 (Default 0xFE) Bit 7 - 1: Reserved. Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. CR24 (Default 0b1s000s0s) Bit 7: EN16SA = 0 12 bit Address Qualification = 1 16 bit Address Qualification Bit 6: EN48 = 0 The clock input on Pin 1 should be 24 Mhz. = 1 The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB (pin 53). -96 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 5 - 3: Reserved. Bit 2: ENKBC = 0 KBC is disabled after hardware reset. = 1 KBC is enabled after hardware reset. This bit is read only, and set/reset by power-on setting pin. The corresponding power-on setting pin is SOUTA (pin 46). Bit 1: Reserved Bit 0: PNPCSV = 0 The Compatible PnP address select registers have default values. = 1 The Compatible PnP address select registers have no default value. When trying to make a change to this bit, new value of PNPCSV must be complementary to the old one to make an effective change. For example, the user must set PNPCSV to 0 first and then reset it to 1 to reset these PnP registers if the present value of PNPCSV is 1. The corresponding power-on setting pin is NDTRA (pin 44). CR25 (Default 0x00) Bit 7 - 6: Reserved Bit 5: URBTRI Bit 4: URATRI Bit 3: PRTTRI Bit 2 - 1 : Reserved Bit 0: FDCTRI. CR26 (Default 0b0s000000) Bit 7: SEL4FDD = 0 Select two FDD mode. = 1 Select four FDD mode. Bit 6: HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is NRTSA (pin 43). HEFRAS Address and Value = 0 Write 87h to the location 3F0h twice. = 1 Write 87h to the location 370h twice. Bit 5: LOCKREG = 0 Enable R/W Configuration Registers. = 1 Disable R/W Configuration Registers. Bit 4: Reserved. Bit 3: DSFDLGRQ = 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ -97 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 2: DSPRLGRQ = 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ = 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ Bit 1: DSUALGRQ = 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Bit 0: DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ CR28 (Default 0x00) Bit 7 - 5: Reserved. Bit 4: IRQ Sharing selection. =0 Disable IRQ Sharing =1 Enable IRQ Sharing Bit 3:Reserved Bit 2 - 0: PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR2A (Default 0x00) Bit 7: PIN57S = 0 KBRST = 1 GP12 Bit 6: PIN56S = 0 GA20 = 1 GP11 Bit 5 - 4: PIN40S1, PIN40S0 = 00 Reserved = 01 GP24 = 10 8042 P13 = 11 Reserved Bit 3 - 2: Reserved. Bit 1 - 0: PIN3S1, PIN3S0 = 00 DRVDEN1 = 01 GP10 = 10 8042 P12 = 11 SCI -98 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CR2B (Default 0x00) Bit 7 - 6: PIN73S1, PIN73S0 = 00 PANSWIN = 01 GP23 = 10 Reserved = 11 Reserved Bit 5: PIN72S PANSWOUT =0 = 1 GP22 Bit 4 - 3: PIN70S1, PIN70S0 = 00 SMI = 01 GP21 = 10 8042 P16 = 11 Reserved Bit 2 - 1: Reserved. Bit 0: PIN58S = 0 KBLOCK = 1 GP13 CR2C (Default 0x00) Bit 7 - 6: PIN121S1, PIN121S0 = 00 DRQ0 = 01 GP17 = 10 8042 P14 = 11 SCI Bit 5 - 4: PIN119S1, PIN119S0 = 00 NDACK0 = 01 GP16 = 10 8042 P15 = 11 Reserved Bit 3 - 2: PIN104S1, PIN104S0 = 00 IRQ15 = 01 GP15 = 10 WDTO = 11 Reserved Bit 1 - 0: PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 Reserved CR2D (Default 0x00) Test Modes: Reserved for Winbond. CR2E (Default 0x00) Test Modes: Reserved for Winbond. CR2F (Default 0x00) Test Modes: Reserved for Winbond. -99 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 11.2 Logical Device 0 (FDC) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit 7 - 3: Reserved. Bit 2 - 0: These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7: FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. = 0 The internal pull-up resistors of FDC are turned on.(Default) = 1 The internal pull-up resistors of FDC are turned off. Bit 6: INTVERTZ This bit determines the polarity of all FDD interface signals. = 0 FDD interface signals are active low. = 1 FDD interface signals are active high. Bit 5: DRV2EN (PS2 mode only) When this bit is a logic 0, this indicates that a second drive is installed and is reflected in status register A. Bit 4: Swap Drive 0, 1 Mode = 0 No Swap (Default) = 1 Drive and Motor sel 0 and 1 are swapped. Bit 3 - 2 Interface Mode = 11 AT Mode (Default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit 1: FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) -100 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 0: Floppy Mode = 0 Normal Floppy Mode (Default) = 1 Enhanced 3-mode FDD CRF1 (Default 0x00) Bit 7 - 6: Boot Floppy = 00 FDD A = 01 FDD B = 10 FDD C = 11 FDD D Bit 5, 4: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit 3 - 2: Density Select = 00 Normal (Default) = 01 Normal = 10 1 ( Forced to logic 1) = 11 0 ( Forced to logic 0) Bit 1: DISFDDWR = 0 Enable FDD write. = 1 Disable FDD write(forces pins WE, WD stay high). Bit 0: SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not. = 1 FDD is always write-protected. CRF2 (Default 0xFF) Bit 7 - 6: FDD D Drive Type Bit 5 - 4: FDD C Drive Type Bit 3 - 2: FDD B Drive Type Bit 1:0: FDD A Drive Type When FDD is in enhanced 3-mode(CRF0.bit0=1),these bits determine SELDEN value in TABLE A of CRF4 and CRF5 as follows. DTYPE1 0 0 0 0 0 1 1 Note: X means don't care. DPYTE0 0 0 0 0 1 0 1 DRATE1 1 0 0 1 X X 0 DRATE0 1 0 1 0 X X 1 SELDEN 1 1 0 0 0 1 0 -101 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CRF4 (Default 0x00) FDD0 Selection: Bit 7: Reserved. Bit 6: Precomp. Disable. = 1 Disable FDC Precompensation. = 0 Enable FDC Precompensation. Bit 5: Reserved. Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). = 00 Select Regular drives and 2.88 format = 01 Specifical application = 10 2 Meg Tape = 11 Reserved Bit 2: Reserved. Bit 1:0: DMOD0, DMOD1 : Drive Model select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. -101.1 - Publication Release Date: July 1997 Revision 0.61 W83977TF PRELIMINARY TABLE A Drive Rate Table Select DRTS1 0 DRTS0 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 Data Rate DRATE1 DRATE0 1 0 1 0 1 0 1 0 1 0 1 0 Selected Data Rate MFM 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K FM --250K 150K 125K --250K 250K 125K --250K --125K SELDEN CRF0 bit 0=0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1. TABLE B DMOD0 0 DMOD1 0 DRVDEN0(pin 2) SELDEN DRVDEN1(pin 3) DRATE0 DRIVE TYPE 4/2/1 MB 3.5" " 2/1 MB 5.25" 2/1.6/1 MB 3.5" (3-MODE) 0 1 1 1 0 1 DRATE1 SELDEN DRATE0 DRATE0 DRATE0 DRATE1 -102- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 11.3 Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base address is on 8 byte boundary). CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for Parallel Port. CR74 (Default 0x04) Bit 7 - 3: Reserved. Bit 2 - 0: These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active CRF0 (Default 0x3F) Bit 7: PP Interrupt Type: Not valid when the parallel port is in the printer Mode (100) or the standard & Bi-directional Mode (000). = 1 Pulsed Low, released to high-Z . = 0 IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP. Bit [6:3]: ECP FIFO Threshold. Bit 2 - 0 Parallel Port Mode = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. -103- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 11.4 Logical Device 2 (UART A)) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7 - 2: Reserved. Bit 1 - 0: SUACLKB1, SUACLKB0 = 00 = 01 = 10 = 11 UART A clock source is 1.8462 Mhz (24MHz/13) UART A clock source is 2 Mhz (24MHz/12) UART A clock source is 24 Mhz (24MHz/1) UART A clock source is 14.769 Mhz (24MHz/1.625) 11.5 Logical Device 3 (UART B) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 2. -104- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CRF0 (Default 0x00) Bit 7 - 4: Reserved. Bit 3: RXW4C =0 =1 No reception delay when SIR is changed from TX mode to RX mode. Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode to RX mode. No transmission delay when SIR is changed from RX mode to TX mode. Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. UART B clock source is 1.8462 Mhz (24MHz/13) UART B clock source is 2 Mhz (24MHz/12) UART B clock source is 24 Mhz (24MHz/1) UART B clock source is 14.769 Mhz (24MHz/1.625) Bit 2: TXW4C =0 =1 Bit 1 - 0: SUBCLKB1, SUBCLKB0 = 00 = 01 = 10 = 11 CRF1 (Default 0x00) Bit 7: Reserved. Bit 6: IRLOCSEL. IR I/O pins' location select. =0 =1 Through SINB/SOUTB. Through IRRX/IRTX. Bit 5: IRMODE2. IR function mode selection bit 2. Bit 4: IRMODE1. IR function mode selection bit 1. Bit 3: IRMODE0. IR function mode selection bit 0. IR MODE 00X 010* 011* 100 101 110 111* IR FUNCTION Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR tri-state IRTX high Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Note: The notation is normal mode in the IR function. -105- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 2: HDUPLX. IR half/full duplex function select. =0 =1 =0 =1 =0 =1 The IR function is Full Duplex. The IR function is Half Duplex. the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. inverse the SOUTB pin of UART B function or IRTX pin of IR function. the SINB pin of UART B function or IRRX pin of IR function in normal condition. inverse the SINB pin of UART B function or IRRX pin of IR function Bit 1: TX2INV. Bit 0: RX2INV. 11.6 Logical Device 5 (KBC) CR30 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x60 if PENKBC= 1 during POR, default 0x00 otherwise) These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x64 if PENKBC= 1 during POR, default 0x00 otherwise) These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary. CR70 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for KINT (keyboard). CR72 (Default 0x0C if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for MINT (PS2 Mouse) CRF0 (Default 0x83) Bit 7 - 6: KBC clock rate selection = 00 Select 6MHz as KBC clock input. = 01 Select 8MHz as KBC clock input. = 10 Select 12Mhz as KBC clock input. = 11 Select 16Mhz as KBC clock input. Bit 5 - 3: Reserved. Bit 2: = 0 Port 92 disable. = 1 Port 92 enable. -106- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 1: = 0 Gate20 software control. = 1 Gate20 hardware speed up. Bit 0: = 0 KBRST software control. = 1 KBRST hardware speed up. 11.7 Logical Device 7 (GP I/O Port I) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select GP1 I/O base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x00) These two registers select GP14 alternate function Primary I/O base address [0x100:0xFFE] on 2 byte boundary; They are available as you setting GP14 to be an alternate function (General Purpose Address Decode). CR64, CR 65 (Default 0x00, 0x00) These two registers select GP15 alternate function Primary I/O base address [0x100:0xFFF] on 1 byte boundary; They are available as you setting GP15 to be an alternate function (General Purpose Write Decode). CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for GP10 as you setting GP10 to be an alternate function (Interrupt Steering). CR72 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for GP11 as you setting GP11 to be an alternate function (Interrupt Steering). CRE0 (GP10, Default 0x01) Bit 7 - 5: Reserved. Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function. = 1 Select Alternate Function: Interrupt Steering. = 0 Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity. = 1 Invert. = 0 No Invert. -107- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 0: In/Out selection. = 1 Input. = 0 Output. CRE1 (GP11, Default 0x01) Bit 7 - 5: Reserved. Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function. = 1 Select Alternate Function: Interrupt Steering. = 0 Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity. = 1 Invert. = 0 No Invert. Bit 0: In/Out selection. = 1 Input. = 0 Output. CRE2 (GP12, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function: Watch Dog Timer Output. = 10 Reserved = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE3 (GP13, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function: Power LED output. = 10 Reserved = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output -108- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CRE4 (GP14, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function: General Purpose Address Decoder(Active Low when Bit 1 = 0, Decode two byte address). = 10 Select 2nd alternate function: Keyboard Inhibit(P17). = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE5 (GP15, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 General Purpose Write Strobe(Active Low when Bit 1 = 0). = 10 8042 P12. = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE6 (GP16, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function: Watch Dog Timer Output. = 1x Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE7 (GP17, Default 0x01) Bit 7 - 4: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function: Power LED output. Please refer to TABLE C = 1x Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output -109- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY TABLE C WDT_CTRL1* BIT[1]* 1 0 0 0 WDT_CTRL0* BIT[3] X 0 1 1 WDT_CTRL1 BIT[0] X X 0 1 POWER LED STATE 1 Hertz Toggle pulse Continuous high or low* Continuous high or low* 1 Hertz Toggle pulse *Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8. 2). Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers. CRF1 ( Default 0x00) General Purpose Read/Write Enable* Bit 7 - 2: Reserved Bit 1: = 1 Enable General Purpose Write Strobe = 0 Disable General Purpose Write Strobe Bit 0: = 1 Enable General Purpose Address Decode = 0 Disable General Purpose Address Decode *Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect. 11.8 Logical Device 8 (GP I/O Port II) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select GP2 & Watch Dog I/O base address [0x100:0xFFE] on 2 byte boundary. I/O base address + 1: Watch Dog I/O base address. CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Common IRQ of GP20~GP26 at Logic Device 8. CR72 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Watch Dog. -110- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CRE8 (GP20, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select basic I/O function = 01 Reserved = 10 Select alternate function: Keyboard Reset (connected to KBC P20) = 11 Reserved Bit 2: Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE9 (GP21, Default 0x01) Bit 7 - 5: Reserved Bit 4 - 3: Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P13 I/O = 11 Reserved Bit 2: Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CREA (GP22, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Reserved = 10 Select 2nd alternate function: Keyboard P14 I/O. = 11 Reserved Bit 2: Int En =1 =0 Enable Common IRQ Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output @ @ -111- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CREB (GP23, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P15 I/O = 11 Reserved Bit 2: Int En =1 =0 Enable Common IRQ Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output @ CREC (GP24, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P16 I/O = 11 Reserved Bit 2: Int En =1 =0 Enable Common IRQ Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRED (GP25, Default 0x01) Bit 7 - 4: Reserved. Bit 3: Select Function. = 1 Select alternate function: GATE A20(Connect to KBC P21). = 0 Select basic I/O function Bit 2: Int En =1 =0 Enable Common IRQ Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output -112- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CREE (GP26, Default 0x01) Bit 7 - 3: Reserved. Bit 2: Int En =1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRF0 (Default 0x00) Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter can reject a pulse with 1ms width or less. Bit 7 - 4: Reserved Bit 3: GP Common IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 2 - 0: Reserved CRF1 (Reserved) CRF2 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any Mouse Interrupt or Keyboard Interrupt happen will also cause to reload the non-zero value to Watch Dog Counter and count down. Read this register can not access Watch Dog Timer Time-out value, but can access the current value in Watch Dog Counter. Bit 7 - 0: = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 minute = 0x02 Time-out occurs after 2 minutes = 0x03 Time-out occurs after 3 minutes ................................................ = 0xFF Time-out occurs after 255 minutes CRF3 (WDT_CTRL0, Default 0x00) Watch Dog Timer Control Register #0 Bit 7 - 4: Reserved Bit 3: When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output. = 1 Enable = 0 Disable Bit 2: Mouse interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Mouse interrupt = 0 Watch Dog Timer is not affected by Mouse interrupt Bit 1: Keyboard interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Keyboard interrupt = 0 Watch Dog Timer is not affected by Keyboard interrupt Bit 0: Reserved. Publication Release Date: March 1998 Revision 0.62 -113- W83977TF PRELIMINARY CRF4 (WDT_CTRL1, Default 0x00) Watch Dog Timer Control Register #1 Bit 7 - 4: Reserved Bit 3: Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W* = 1 Enable = 0 Disable Bit 2: Force Watch Dog Timer Time-out, Write only* = 1 Force Watch Dog Timer time-out event; this bit is self-clearing. Bit 1: Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W = 1 Enable = 0 Disable Bit 0: Watch Dog Timer Status, R/W = 1 Watch Dog Timer time-out occurred. = 0 Watch Dog Timer counting *Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us. 2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then connect to set the Bit 0(Watch Dog Timer Status). The ORed signal is self-clearing. 11.9 Logical Device 9 (GP I/O Port III) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select GP3 I/O base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x00) These two registers select GP32 alternate function Primary I/O base address [0x100:0xFFE] on 2byte boundary; They are available as you setting GP32 to be an alternate function (General Purpose Address Decode). CR64, CR 65 (Default 0x00, 0x00) These two registers select GP33 alternate function Primary I/O base address [0x100:0xFFF] on 2byte boundary; They are available as you setting GP33 to be an alternate function (General Purpose Address Decode). CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for GP30 as you setting GP30 to be an alternate function (Interrupt Steering). CR72 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for GP31 as you setting GP31 to be an alternate function (Interrupt Steering). -114- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CRE0 (GP30, Default 0x01) Bit 7 - 5: Reserved. Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled. = 0 Debounce Filter Bypassed. Bit 3: Select Function. = 1 Select Alternate Function: Interrupt Steering. = 0 Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity. = 1 Invert. = 0 No Invert. Bit 0: In/Out selection. = 1 Input. = 0 Output. CRE1 (GP31, Default 0x01) Bit 7 - 5: Reserved. Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function. = 1 Select Alternate Function: Interrupt Steering. = 0 Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity. = 1 Invert. = 0 No Invert. Bit 0: In/Out selection. = 1 Input. = 0 Output. CRE2 (GP32, Default 0x01) Bit 7 - 4: Reserved. Bit 3: Select Function. = 1 Select Alternate Function: General Purpose Address Decode. = 0 Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE3 (GP33, Default 0x01) Bit 7 - 4: Reserved. Bit 3: Select Function. = 1 Select Alternate Function: General Purpose Address Decode. = 0 Select Basic I/O Function. Publication Release Date: March 1998 Revision 0.62 -115- W83977TF PRELIMINARY Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE4 (GP34, Default 0x01) Bit 7 - 4: Reserved. Bit 3: Select Function. = 1 Select Alternate Function: Watch Dog Timer output. = 0 Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE5 (GP35, Default 0x01) Bit 7 - 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE6 (GP36, Default 0x01) Bit 7 - 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE7 (GP37, Default 0x01) Bit 7 - 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRF1 ( Default 0x00) Bit 7 - 3: Reserved Bit 2: SERIRQ = 0 The IRQ system is in normal mode. = 1 The IRQ system is in serial IRQ mode. Bit 1: = 1 Enable GP33 General Purpose Address Decode. = 0 Disable GP33 General Purpose Address Decode. Bit 0: = 1 Enable GP32 General Purpose Address Decode. = 0 Disable GP32 General Purpose Address Decode. *Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect. -116- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 11.10 Logical Device A (ACPI) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select PM1 register block base address [0x100:0xFF0] on 16-byte boundary. CR62, CR 63 (Default 0x00, 0x00) These two registers select GPE0 register block base address [0x100:0xFFC] on 4-byte boundary. CR64, CR 65 (Default 0x00, 0x00) These two registers select GPE1 register block base address [0x100:0xFFC] on 4-byte boundary. CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for SCI . CRE0 (Default 0x00) Bit 7: DIS-PANSWIN. Disable panel switch input to turn system power supply on. =0 =1 PANSWIN is wire-ANDed and connected to PANSWOUT . PANSWIN is blocked and can not affect PANSWOUT . Bit 6: ENKBWAKEUP. Enable Keyboard to wake-up system via PANSWOUT . =0 =1 Disable Keyboard wake-up function. Enable Keyboard wake-up function. Bit 5: ENMSWAKEUP. Enable Mouse to wake-up system via PANSWOUT . =0 =1 Disable Mouse wake-up function. Enable Mouse wake-up function. Bit 4: MSRKEY. Select Mouse Left/Right Botton to wake-up system via PANSWOUT . =0 =1 Select click on Mouse Left-botton twice to wake the system up. Select click on Mouse right-botton twice to wake the system up. Bit 3: Reserved. Bit 2: KB/MS Swap. Enable Keyboard/Mouse port-swap. =0 =1 =0 =1 Keyboard/Mouse ports are not swapped. Keyboard/Mouse ports are swapped. Just clicking Mouse left/right-botton twice can wake the system up. Any character received from Mouse can wake the system up (the setting of Bit 4 is ignored). Bit 1: MSXKEY. Enable any character received from Mouse to wake-up the system. -117- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 0: KBXKEY. Enable any character received from Keyboard to wake-up the system. =0 =1 Only predetermined specific key combination can wake up the system. Any character received from Keyboard can wake up the system. CRE1 (Default 0x00) Keyboard Wake-up Index Register This register is used to indicate which Keyboard Wake-up Shift register or Predetermined key Register is to be read/written via CRE2. CRE2 Keyboard Wake-up Data Register CRE3 (Read only) Keyboard/Mouse Wake-up Status Register Bit 7-3: Reserved. Bit 2: PANSW_STS. The Panel switch event is caused by PANSWIN . This bit is cleared by reading this register. Bit 1: Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. Bit 0: Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. CRE4 This Register is reserved for test. CRF0 (Default 0x00) Bit 7: CHIPPME. Chip level power management enable. =0 =1 disable the ACPI/Legacy and the auto power management functions enable the ACPI/Legacy and the auto power management functions. Bit 6 - 4: Reserved. Return zero when read. Bit 3: PRTPME. Printer port power management enable. =0 =1 disable the auto power management functions. enable the auto power management functions provided CRF0.bit7 (CHIPPME) is also set to 1. disable the auto power management functions. enable the auto power management functions provided CRF0.bit7 (CHIPPME) is also set to 1. disable the auto power management functions. enable the auto power management functions provided CRF0.bit7 (CHIPPME) is also set to 1. disable the auto power management functions. enable the auto power management functions provided CRF0.bit7 (CHIPPME) is also set to 1. Bit 2: FDCPME. FDC power management enable. =0 =1 Bit 1: URAPME. UART A power management enable. =0 =1 Bit 0: URBPME. UART B power management enable. =0 =1 -118- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY CRF1 (Default 0x00) Bit 7 - 4: Reserved. Return zero when read. Bit 3 - 0: Devices' idle status. These bits indicate that the individual device's idle timer expires due to no I/O access, no IRQ, and no external input to the device. These 4 bits are controlled by the printer port, FDC, UART A, and UART B power down machines individually. Writing a 1 clears this bit, and writing a 0 has no effect. Note that: the user is not supposed to change the status while the power management function is enabled. Bit 3: PRTIDLSTS. Printer port idle status. =0 =1 printer port is now in the working state. printer port is now in the sleeping state due to no printer port access, no IRQ, no DMA acknowledge, and no transition on BUSY, ACK , PE, SLCT, and ERR pins in a preset expiry time period. FDC is now in the working state. FDC is now in the sleeping state due to no FDC access, no IRQ, no DMA acknowledge, and no enabling of the motor enable bits in the DOR register in a preset expiry time period. UART A is now in the working state. UART A is now in the sleeping state due to no UART A access, no IRQ, the receiver is now waiting for a start bit, the transmitter shift register is now empty, and no transition on MODEM control input lines in a preset expiry time period. UART B is now in the working state. UART B is now in the sleeping state due to no UART A access, no IRQ, the receiver is now waiting for a start bit, the transmitter shift register is now empty, and no transition on MODEM control input lines in a preset expiry time period. Bit 2: FDCIDLSTS. FDC idle status. =0 =1 Bit 1: URAIDLSTS. UART A idle status. =0 =1 Bit 0: URBIDLSTS. UART B idle status. =0 =1 CRF2 (Default 0x00) Bit 7 - 4: Reserved. Return zero when read. Bit 3 - 0: Devices' trap status. These bits indicate that the individual device wakes up due to any I/O access, IRQ, and external input to the device. The device's idle timer reloads the preset expiry depending on which device wakes up. These 4 bits are controlled by the printer port, FDC, UART A, and UART B power down machines respectively. Writing a 1 clears this bit, and writing a 0 has no effect. Note that: the user is not supposed to change the status while power management function is enabled. Bit 3: PRTTRAPSTS. Printer port trap status. =0 =1 the printer port is now in the sleeping state. the printer port is now in the working state due to any printer port access, any IRQ, any DMA acknowledge, and any transition on BUSY, ACK , PE, SLCT, and ERR pins. -119- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 2: FDCTRAPSTS. FDC trap status. =0 =1 FDC is now in the sleeping state. FDC is now in the working state due to any FDC access, any IRQ, any DMA acknowledge, and any enabling of the motor enable bits in the DOR register. UART A is now in the sleeping state. UART A is now in the working state due to any UART A access, any IRQ, the receiver begins receiving a start bit, the transmitter shift register begins transmitting a start bit, and any transition on MODEM control input lines. UART B is now in the sleeping state. UART B is now in the working state due to any UART B access, any IRQ, the receiver begins receiving a start bit, the transmitter shift register begins transmitting a start bit, and any transition on MODEM control input lines. Bit 1: URATRAPSTS. UART A trap status. =0 =1 Bit 0: URBTRAPSTS. UART B trap status. =0 =1 CRF3 (Default 0x00) Bit 7 - 6: Reserved. Return zero when read. Bit 5 - 0: Device's IRQ status. These bits indicate the IRQ status of the individual device. The device's IRQ status by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 5: MOUIRQSTS. MOUSE IRQ status. Bit 4: KBCIRQSTS. KBC IRQ status. Bit 3: PRTIRQSTS. printer port IRQ status. Bit 2: FDCIRQSTS. FDC IRQ status. Bit 1: URAIRQSTS. UART A IRQ status. Bit 0: URBIRQSTS. UART B IRQ status. CRF4 (Default 0x00) Bit 7 - 4: Reserved. Return zero when read. Bit 3 - 0: Enable bits of the SMI generation due to the device's idleness. These bits enable the generation of an SMI interrupt due to the expiration of the device's idle timer. These 4 bits control the printer port, FDC, UART A, and UART B SMI logics respectively. Bit 3: PRTIDLEN. =0 =1 disable the generation of an SMI interrupt due to printer port's idleness. enable the generation of an SMI interrupt due to printer port's idleness. bit is set Bit 2: FDCIDLEN. =0 =1 disable the generation of an SMI interrupt due to FDC's idleness. enable the generation of an SMI interrupt due to FDC's idleness. -120- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 1: URAIDLEN. =0 =1 disable the generation of an SMI interrupt due to UART A's idleness. enable the generation of an SMI interrupt due to UART A's idleness. Bit 0: URBIDLEN. =0 =1 disable the generation of an SMI interrupt due to UART B's idleness. enable the generation of an SMI interrupt due to UART B's idleness. CRF5 (Default 0x00) Bit 7 - 4: Reserved. Return zero when read. Bit 3 - 0: Enable bits of the SMI generation due to device's trap. These bits enable the generation of an SMI interrupt due to any I/O access, IRQ, and external input to the device. These 4 bits control the printer port, FDC, UART A, and UART B SMI logics respectively. Bit 3: PRTTRAPEN. =0 =1 disable the generation of an SMI interrupt due to printer port's trap. enable the generation of an SMI interrupt due to printer port's trap. Bit 2: FDCTRAPEN. =0 =1 disable the generation of an SMI interrupt due to FDC's trap. enable the generation of an SMI interrupt due to FDC's trap. Bit 1: URATRAPEN. =0 =1 disable the generation of an SMI interrupt due to UART A's trap. enable the generation of an SMI interrupt due to UART A's trap. Bit 0: URBTRAPEN. =0 =1 disable the generation of an SMI interrupt due to UART B's trap. enable the generation of an SMI interrupt due to UART B's trap. CRF6 (Default 0x00) Bit 7 - 6: Reserved. Return zero when read. Bit 5 - 0: Enable bits of the SMI generation due to the device's IRQ. These bits enable the generation of an SMI interrupt due to any IRQ of the devices. These 4 bits control the printer port, FDC, UART A, and UART B SMI logics respectively. The SMI logic output for the IRQs is as follows: SMI logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS) (KBCIRQEN and KBCIRQSTS) or (MOUIRQEN and MOUIRQSTS) -121- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY Bit 5: MOUIRQEN. =0 =1 disable the generation of an SMI interrupt due to MOUSE's IRQ. enable the generation of an SMI interrupt due to MOUSE's IRQ. Bit 4: KBCIRQEN. =0 =1 disable the generation of an SMI interrupt due to KBC's IRQ. enable the generation of an SMI interrupt due to KBC's IRQ. Bit 3: PRTIRQEN. =0 =1 disable the generation of an SMI interrupt due to printer port's IRQ. enable the generation of an SMI interrupt due to printer port's IRQ. Bit 2: FDCIRQEN. =0 =1 disable the generation of an SMI interrupt due to FDC's IRQ. enable the generation of an SMI interrupt due to FDC's IRQ. Bit 1: URAIRQEN. =0 =1 disable the generation of an SMI interrupt due to UART A's IRQ. enable the generation of an SMI interrupt due to UART A's IRQ. Bit 0: URBIRQEN. =0 =1 disable the generation of an SMI interrupt due to UART B's IRQ. enable the generation of an SMI interrupt due to UART B's IRQ. CRF7 (Default 0x00) Bit 7 - 1: Reserved. Return zero when read. Bit 0: SMI_EN. This bit is the SMI output pin enable bit. When an SMI event is raised on the output of the SMI logic, setting this bit enables the SMI interrupt to be generated on the pin SMI . If this bit is cleared, only the IRQ status bit in CRF3 is set, and no SMI interrupt is generated on the pin SMI . =0 =1 Disable SMI Enable SMI CRFE, FF (Default 0x00) Reserved for Winbond test. -122- Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.0 SPECIFICATIONS 12.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage Battery Voltage VBAT Operating Temperature Storage Temperature RATING -0.5 to 7.0 -0.5 to VDD+0.5 4.0 to 1.8 0 to +70 -55 to +150 UNIT V V V C C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 12.2 DC CHARACTERISTICS (Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) PARAMETER Battery Quiescent Current Stand-by Power Supply Quiescent Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage SYM. IBAT IBAT MIN. TYP. MAX. 2.4 2.0 UNIT uA mA CONDITIONS VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected. I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 8 mA IOH = - 8 mA VIN = VDD VIN = 0V I/O6t - TTL level bi-directional pin with source-sink capability of 6 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 6 mA IOH = - 6 mA VIN = VDD VIN = 0V - 123 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.2 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O8 - CMOS level bi-directional pin with source-sink capability of 8 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V A A IOL = 8 mA IOH = - 8 mA VIN = VDD VIN = 0V I/O12 - CMOS level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V A A IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V I/O16u - CMOS level bi-directional pin with source-sink capability of 16 mA, with internal pull-up resistor Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V A A IOL = 16 mA IOH = - 16 mA VIN = VDD VIN = 0V I/OD16u - CMOS level Open-Drain pin with source-sink capability of 16 mA, with internal pull-up resistor Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V A A IOL = 16 mA IOH = - 16 mA VIN = VDD VIN = 0V - 124 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.2 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 + 10 - 10 2.0 0.4 0.8 V V V V A A IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V I/O24t - TTL level bi-directional pin with source-sink capability of 24 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 + 10 - 10 2.0 0.4 0.8 V V V V A A IOL = 24 mA IOH = - 24 mA VIN = VDD VIN = 0V OUT8t - TTL level output pin with source-sink capability of 8 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 8 mA IOH = - 8 mA OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V IOL = 12 mA OD24 - Open-drain output pin with sink capability of 24 mA Output Low Voltage VOL 0.4 V IOL = 24 mA INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = VDD VIN = 0 V - 125 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.2 DC CHARACTERISTICS, continued PARAMETER INc - CMOS level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 0.7xVDD +10 -10 0.3xVDD V V A A VIN = VDD VIN = 0 V SYM. MIN. TYP. MAX. UNIT CONDITIONS INcs - CMOS level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 +10 -10 1.7 3.8 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V INcu - CMOS level input pin with internal pull-up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 0.7xVDD +10 -10 0.7xVDD V V A A VIN = VDD VIN = 0 V INts - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V - 126 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.3 AC Characteristics 12.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. PARAMETER SA9-SA0, AEN, DACK , CS , setup time to IOR o SA9-SA0, AEN, DACK , hold time for IOR o IOR width Data access time from IOR o Data hold from IOR o SD to from IOR o IRQ delay from IOR o SA9-SA0, AEN, DACK , setup time to IOW o SA9-SA0, AEN, DACK , hold time for IOW o IOW width Data setup time to IOW o Data hold time from IOW o IRQ delay from IOW o DRQ cycle time DRQ delay time DACK o DRQ to DACK delay DACK width IOR delay from DRQ IOW delay from DRQ SYM. TAR TAR TRR TFD TDH TDF TRI TAW TWA TWW TDW TWD TWI TMCY TAM TMA TAA TMR TMW TEST CONDITIONS MIN. 25 0 80 TYP. (NOTE 1) MAX. UNIT nS nS nS CL = 100 pf CL = 100 pf CL = 100 pf 10 10 80 nS nS 50 360/570 /675 nS nS nS nS nS nS nS 25 0 60 60 0 360/570 /675 27 50 0 260/430 /510 0 0 nS S nS nS nS nS nS - 127 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.3.1 AC Characteristics, FDC continued PARAMETER IOW or IOR response time from DRQ TC width RESET width INDEX width DIR setup time to STEP DIR hold time from STEP STEP pulse width STEP cycle width SYM. TMRW TTC TRST TIDX TDST TSTD TSTP TSC TWDD TWPC TEST CONDITIONS MIN. TYP. (NOTE 1) 6/12 /20/24 MAX. UNIT S nS S S S S 135/220 /260 1.8/3/3. 5 0.5/0.9 /1.0 1.0/1.6 /2.0 24/40/48 6.8/11.5 /13.8 Note 2 100/185 /225 100/138 /225 7/11.7 /14 Note 2 125/210 /250 125/210 /250 7.2/11.9 /14.2 Note 2 150/235 /275 150/235 /275 S S S S WD pulse width Write precompensation Notes: 1. Typical values for T = 25 C and normal supply voltage. 2. Programmable from 2 mS through 32 mS in 2 mS increments. - 128 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.3.2 UART/Parallel Port PARAMETER Delay from Stop to Set Interrupt Delay from IOR Reset Interrupt Delay from Initial IRQ Reset to Transmit Start Delay from IOW to Reset interrupt Delay from Initial IOW to interrupt Delay from Stop to Set Interrupt Delay from IOR to Reset Interrupt Delay from IOR to Output Set Interrupt Delay from Modem Input Reset Interrupt Delay from IOR Interrupt Active Delay Interrupt Inactive Delay Baud Divisor SYMBOL TSINT TRINT TIRS THR TSI TSTI TIR TMWO TSIM TRIM TIAD TIID N TEST CONDITIONS MIN. 9/16 MAX. UNIT Baud Rate 100 pf Loading 1/16 100 pf Loading 9/16 1 8/16 175 16/16 1/2 S Baud Rate nS Baud Rate Baud Rate nS nS nS nS nS nS 100 pF Loading 100 pF Loading 250 200 250 250 100 pF Loading 100 pF Loading 100 pF Loading 25 30 216-1 12.3.3 Parallel Port Mode Parameters PARAMETER PD0-7, INDEX, STROBE, AUTOFD Delay from IOW IRQ Delay from ACK , nFAULT IRQ Delay from IOW IRQ Active Low in ECP and EPP Modes ERROR Active to IRQ Active SYM. t1 t2 t3 t4 t5 MIN. TYP. MAX. 100 60 105 UNIT nS nS nS nS nS 200 300 105 - 129 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.3.4 EPP Data or Address Read Cycle Timing Parameters PARAMETER Ax Valid to IOR Asserted IOCHRDY Deasserted to IOR Deasserted IOR Deasserted to Ax Valid IOR Deasserted to IOW or IOR Asserted IOR Asserted to IOCHRDY Asserted PD Valid to SD Valid IOR Deasserted to SD Hi-Z (Hold Time) SD Valid to IOCHRDY Deasserted WAIT Deasserted to IOCHRDY Deasserted PD Hi-Z to PDBIR Set WRITE Deasserted to IOR Asserted WAIT Asserted to WRITE Deasserted SYM. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 MIN. 40 0 10 40 0 0 0 0 60 0 0 0 60 0 60 0 0 60 1 0 0 0 60 10 0 0 MAX. UNIT nS nS 10 nS 24 75 40 85 160 nS nS S nS nS nS nS 185 190 50 180 nS nS nS nS nS nS Deasserted to WRITE Modified IOR Asserted to PD Hi-Z WAIT Asserted to PD Hi-Z Command Asserted to PD Valid Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted 190 nS nS 20 30 195 180 12 nS nS nS nS nS nS S WAIT Deasserted to Command Deasserted Time out PD Valid to WAIT Deasserted PD Hi-Z to WAIT Deasserted - 130 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.3.5 EPP Data or Address Write Cycle Timing Parameters PARAMETER Ax Valid to IOW Asserted SD Valid to Asserted IOW Deasserted to Ax Invalid WAIT Deasserted to IOCHRDY Deasserted Command Asserted to WAIT Deasserted IOW Deasserted to IOW or IOR Asserted IOCHRDY Deasserted to IOW Deasserted WAIT Asserted to Command Asserted IOW Asserted to WAIT Asserted SYM. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 MIN. 40 10 10 0 10 40 0 60 0 0 60 60 0 0 10 5 60 60 0 10 0 0 MAX. UNIT nS nS nS nS nS nS 24 160 70 nS nS nS nS PBDIR Low to WRITE Asserted WAIT Asserted to WRITE Asserted WAIT Asserted to WRITE Change IOW Asserted to PD Valid WAIT Asserted to PD Invalid PD Invalid to Command Asserted IOW to Command Asserted WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted Command Asserted to WAIT Deasserted Time out Command Deasserted to WAIT Asserted 185 185 50 nS nS nS nS nS 35 210 190 10 12 nS nS nS S S nS nS IOW Deasserted to WRITE Deasserted and PD invalid - 131 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.3.6 Parallel Port FIFO Timing Parameters PARAMETER DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active SYMBOL t1 t2 t3 t4 t5 t6 MIN. 600 600 450 80 680 500 MAX. UNIT nS nS nS nS nS nS 12.3.7 ECP Parallel Port Forward Timing Parameters PARAMETER nAUTOFD Valid to nSTROBE Asserted PD Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed BUSY Deasserted to PD Changed nSTROBE Deasserted to BUSY Deasserted BUSY Deasserted to nSTROBE Asserted nSTROBE Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 MIN. 0 0 80 80 0 80 0 80 180 200 MAX. 60 60 180 180 UNIT nS nS nS nS nS nS nS nS 12.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted SYMBOL t1 t2 t3 t4 t5 t6 MIN. 0 0 0 0 80 80 MAX. UNIT nS nS nS nS 200 200 nS nS - 132 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.3.9 KBC Timing Parameters NO. T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 DESCRIPTION Address Setup Time from WRB Address Setup Time from RDB WRB Strobe Width RDB Strobe Width Address Hold Time from WRB Address Hold Time from RDB Data Setup Time Data Hold Time Gate Delay Time from WRB RDB to Drive Data Delay RDB to Floating Data Delay Data Valid After Clock Falling (SEND) K/B Clock Period K/B Clock Pulse Width Data Valid Before Clock Falling (RECEIVE) K/B ACK After Finish Receiving RC Fast Reset Pulse Delay (8 Mhz) RC Pulse Width (8 Mhz) Transmit Timeout Data Valid Hold Time Input Clock Period (6-12 Mhz) Duration of CLK inactive Duration of CLK active Time from inactive CLK transition, used to time when the auxiliary device sample DATA Time of inhibit mode Time from rising edge of CLK to DATA transition Duration of CLK inactive Duration of CLK active Time from DATA transition to falling edge of CLK 0 83 30 30 5 100 5 30 30 5 167 50 50 25 300 T28-5 50 50 25 20 10 4 20 2 6 2 3 0 MIN. 0 0 20 20 0 0 50 0 10 30 40 20 4 MAX. UNIT nS nS nS nS nS nS nS nS nS nS nS S S S S S S S mS S nS S S S S S S S S - 133 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 12.3.10 GPIO Timing Parameters SYMBOL tWGO PARAMETER Write data to GPIO update MIN. MAX. 300(Note 1) UNIT ns Note : Refer to Microprocessor Interface Timing for Read Timing. 12.3.11 Keyboard/Mouse Timing Parameters SYMBOL tSWL tSWH tWKUPD tWKUPW PARAMETER PANSWIN falling edge to PANSWOUT falling edge PANSWIN falling edge to PANSWOUT Hi-Z MIN. MAX. 20 50 200 UNIT ns ns ns sec KCLK/MCLK falling edge to PANSWOUT falling edge delay PANSWOUT active pulse width 0.5 1 - 134 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.0 TIMING WAVEFORMS 13.1 FDC Processor Read Operation SA0-SA9 AEN CS DACK TRR IOR TFD TDF D0-D7 INDEX TR IRQ TIDX TDH TAR TRA WD Write Date TWDD Index TIDX Processor Write Operation SA0-SA9 AEN DACK IOW TWD TAW TWW TWA TC Terminal Count TTC Reset TDW D0-D7 RESET TWI IRQ TRST DMA Operation Drive Seek operation TAM DRQ DIR TMCY DACK TMA IOW or IOR TMW (IOW) TMR (IOR) TSC TMRW STEP TAA TDST TSTP TSTD - 135 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.2 UART/Parallel Receiver Timing SIN (RECEIVER INPUT DATA) STAR DATA BITS (5-8) PARITY STOP TSINT IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER) TRINT Transmitter Timing SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) THR TSI STAR DATA (5-8) PARITY STOP (1-2) STAR TSTI TIR IOR (READ TIR) - 136 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.2.1 Modem Control Timing MODEM Control Timing IOW (WRITE MCR) RTS,DTR / x x x x x x x x x x x x o TMWO x x x / x x x x x x x x oTMWO CTS,DSR DCD IRQ3 or IRQ4 IOR (READ MSR) o / x TSIM x x x x x / / oTRIM x x x x x x x o TSIM / oTRIM TSIM o / x x x x x x x x x x x x x x x x x x x x x x x RI Printer Interrupt Timing x x x x x x x x x x x ACK / IRQ7 x x x x x o TLAD / x x x x x o TLID - 137 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.3 Parallel Port 13.3.1 Parallel Port Timing IOW t1 INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK t2 IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) t5 t2 IRQ t4 t3 t4 - 138 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) t3 A<0:10> IOR t1 t6 SD<0:7> t8 t5 IOCHRDY t10 t9 t2 t7 t4 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 t24 t25 t15 t18 t19 t20 ADDRSTB DATASTB t26 t27 t28 WAIT - 139 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.3.3 EPP Data or Address Write Cycle (EPP Version 1.9) t3 t4 A10-A0 SD<0:7> t1 IOW IOCHRDY t9 t10 t11 t13 t15 t16 t17 DATAST ADDRSTB t19 t20 WAIT t22 PBDIR t21 t2 t7 t8 t5 t6 t12 t14 WRITE PD<0:7> t18 - 140 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) t3 A<0:10> IOR t1 t6 t7 SD<0:7> t8 t5 IOCHRDY t10 t9 t2 t4 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 t25 t24 t15 t18 t19 t20 ADDRSTB DATASTB t26 t27 t28 WAIT - 141 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.3.5 EPP Data or Address Write Cycle (EPP Version 1.7) t3 t4 A10-A0 SD<0:7> t1 IOW IOCHRDY t9 t10 t11 t13 t15 t16 t17 DATAST ADDRSTB t19 t20 WAIT t2 t7 t8 t5 t6 t22 t22 WRITE PD<0:7> t18 13.3.6 Parallel Port FIFO Timing t4 t3 PD<0:7> t1 nSTROBE >| t2 > t5 >| >| >| t6 BUSY >| - 142 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.3.7 ECP Parallel Port Forward Timing t3 nAUTOFD t4 PD<0:7> t1 t2 t6 nSTROBE t5 BUSY t7 t5 t8 13.3.8 ECP Parallel Port Reverse Timing t2 PD<0:7> t1 t3 nACK t5 nAUTOFD t6 t5 t4 - 143 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.4 KBC 13.4.1 Write Cycle Timing A2, CSB T1 T3 ACTIVE T7 T8 T5 WRB D0~D7 GA20 OUTPUT PORT FAST RESET PULSE RC FE COMMAND DATA IN T9 T17 T18 13.4.2 Read Cycle Timing A2,CSB AEN T2 T4 T6 RDB ACTIVE T10 T11 D0-D7 DATA OUT 13.4.3 Send Data to K/B CLOCK (KCLK) T12 T14 D1 D2 D3 T13 D4 T19 D5 D6 D7 P STOP T16 SERIAL DATA (KDAT) START D0 - 144 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.4.4 Receive Data from K/B CLOCK (KCLK) T15 T14 D0 D1 D2 D3 D4 T13 D5 D6 D7 P SERIAL DATA (T1) START T20 STOP 13.4.5 Input Clock CLOCK CLOCK T21 13.4.6 Send Data to Mouse MCLK T25 T22 T23 T24 MDAT START Bit D0 D1 D2 D3 D4 D5 D6 D7 P STOP Bit 13.4.7 Receive Data from Mouse MCLK T29 T26 T27 T28 MDAT START D0 D1 D2 D3 D4 D5 D6 D7 P STOP Bit - 145 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 13.5 GPIO Write Timing Diagram A0-A15 IOW D0-7 GPIO10-17 GPIO20-25 PREVIOUS STATE VALID VALID VALID tWGO 13.6 Master Reset (MR) Timing Vcc tVMR MR 13.7 Keyboard/Mouse Wake-up Timing KCLK MCLK PANSWIN PANSWOUT HI-Z tWKUPD tSWL tSWZ tWKUPW - 146 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 14.0 APPLICATION CIRCUITS 14.1 Parallel Port Extension FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram 14.2 Parallel Port Extension 2FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension 2FDD Connection Diagram - 147 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 14.3 Four FDD Mode 74LS139 W83977F DSA DSB MOA MOB G2 A2 B2 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 DSA DSB DSC DSD MOA MOB MOC MOD 7407(2) 15.0 ORDERING INFORMATION PART NO. W83977TF-P W83977TF-A W83977TF-PW W83977TF-AW KBC FIRMWARE Phoenix MultiKey/42 AMIKEY TM TM REMARKS -2 TM Phoenix MultiKey/42 AMIKEY TM with OnNow / security keyboard wake-up with OnNow / security keyboard wake-up -2 16.0 HOW TO READ THE TOP MARKING Example: The top marking of W83977TF-A inbond W83977TF-A (c) AM. MEGA. 87-96 730AC2722968SA 1st line: Winbond logo 2nd line: the type number: W83977TF-A TM 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code 730 A C 2 722968 SA 730: packages made in '97, week 30 A: assembly house ID; A means ASE, S means SPIL.... etc. C: IC revision; B means version B, C means version C 2: wafers manufactured in Winbond FAB 2 722968: wafer production series lot number SA: if made by 0.5-um process: SA; otherwise by 0.6-um process: blank - 148 - Publication Release Date: March 1998 Revision 0.62 W83977TF PRELIMINARY 17.0 PACKAGE DIMENSIONS (128-pin PQFP) HE E 102 65 Symbol Min Dimension in mm Dimension in inch Nom 0.35 2.72 0.20 0.15 14.00 20.00 0.50 Max 0.45 2.87 0.30 0.20 14.10 20.10 Min 0.010 0.101 0.004 0.004 0.547 0.783 Nom 0.014 0.107 0.008 0.006 0.551 0.787 0.020 Max 0.018 0.113 0.012 0.008 0.555 0.791 103 64 D HD 128 39 1 e 38 b A1 A2 b c D E e HD HE L L1 y 0 c 0.25 2.57 0.10 0.10 13.90 19.90 17.00 23.00 0.65 17.20 23.20 0.80 1.60 17.40 23.40 0.95 0.669 0.905 0.025 0.677 0.913 0.031 0.063 0.685 0.921 0.037 0.08 0 7 0 0.003 7 Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. A A2 See Detail F Seating Plane A1 y L L1 Detail F 5. PCB layout please use the "mm". Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their original owners. Publication Release Date: March 1998 Revision 0.62 - 149 - |
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